This paper investigates the trap analysis of a double-gate extended-source tunnel field-effect transistor (DG-ESTFET) and single-gate extended-source tunnel field-effect transistor (SG-ESTFET) with a δp⁺ SiGe pocket layer. The trap analysis of both structures is compared in terms of the currents, average subthreshold swing, threshold voltage, and switching ratio. In addition, the impact of interface trap charges at different interfaces on analog/RF performance, transfer characteristics, and slope are investigated and compared. It is observed that the trap charges between the silicon and front gate oxide interface (Si–HfO₂) have a greater effect on the DG-ESTFET than the SG-ESTFET, whereas the reverse is true when trap charges are at the back gate oxide interface (Si–SiO₂). In the case of analog/RF performance, the SG-ESTFET is found to be more affected by the trap charges at the silicon and front gate oxide interface (Si–HfO₂).

本文研究了具有δp ⁺ SiGe口袋层的双栅扩展源隧道隧穿效应晶体管（DG-ESTFET）和单栅扩展源隧道隧穿效应晶体管（SG-ESTFET）的陷阱分析。根据电流，平均亚阈值摆幅，阈值电压和开关比对两种结构的陷阱分析进行了比较。此外，还研究并比较了不同接口处的接口陷阱电荷对模拟/ RF性能，传输特性和斜率的影响。可以观察到，硅和前栅极氧化物界面（Si–HfO ₂）之间的陷阱电荷对DG-ESTFET的影响大于SG-ESTFET，而当陷阱电荷位于后栅极氧化物处时，情况相反界面（Si–SiO ₂）。在模拟/ RF性能的情况下，发现SG-ESTFET受硅和前栅极氧化物界面（Si–HfO ₂）处陷阱电荷的影响更大。