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Comparative Analysis of the Effects of Trap Charges on Single- and Double-Gate Extended-Source Tunnel FET with δp+ SiGe Pocket Layer

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Abstract

This paper investigates the trap analysis of a double-gate extended-source tunnel field-effect transistor (DG-ESTFET) and single-gate extended-source tunnel field-effect transistor (SG-ESTFET) with a δp+ SiGe pocket layer. The trap analysis of both structures is compared in terms of the currents, average subthreshold swing, threshold voltage, and switching ratio. In addition, the impact of interface trap charges at different interfaces on analog/RF performance, transfer characteristics, and slope are investigated and compared. It is observed that the trap charges between the silicon and front gate oxide interface (Si–HfO2) have a greater effect on the DG-ESTFET than the SG-ESTFET, whereas the reverse is true when trap charges are at the back gate oxide interface (Si–SiO2). In the case of analog/RF performance, the SG-ESTFET is found to be more affected by the trap charges at the silicon and front gate oxide interface (Si–HfO2).

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, NIT Silchar, Assam, Silchar, India

    Jagritee Talukdar & Kavicharan Mummaneni

  2. Department of Electronics and Communication Engineering, NIT Hamirpur, Hamirpur, India

    Gopal Rawat

  3. Department of Electronics and Communication Engineering, NIT Jamshedpur, Jamshedpur, India

    Kunal Singh

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  1. Jagritee Talukdar
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  2. Gopal Rawat
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  3. Kunal Singh
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  4. Kavicharan Mummaneni
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Correspondence to Jagritee Talukdar.

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Talukdar, J., Rawat, G., Singh, K. et al. Comparative Analysis of the Effects of Trap Charges on Single- and Double-Gate Extended-Source Tunnel FET with δp+ SiGe Pocket Layer. J. Electron. Mater. 49, 4333–4342 (2020). https://doi.org/10.1007/s11664-020-08151-5

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  • DOI: https://doi.org/10.1007/s11664-020-08151-5

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