CMOS technology scaling has reached its limit at the 22 nm technology node due to several factors including Process Variations (PV), increased leakage current, Random Dopant Fluctuation (RDF), and mainly the Short-Channel Effect (SCE). In order to continue the miniaturization process via technology down-scaling while preserving system reliability and performance, Fin Field-Effect Transistors (FinFETs) arise as an alternative to CMOS transistors. In parallel, Static Random-Access Memories (SRAMs) increasingly occupy great part of Systems-on-Chips’ (SoCs) silicon area, making their reliability an important issue. SRAMs are designed to reach densities at the limit of the manufacturing process, making this component susceptible to manufacturing defects, including the resistive ones. Such defects may cause dynamic faults during the circuits’ lifetime, an important cause of test escape. Thus, the identification of the proper faulty behavior taking different operating conditions into account is considered crucial to guarantee the development of more suitable test methodologies. In this context, a comparison between the behavior of a 22 nm CMOS-based and a 20 nm FinFET-based SRAM in the presence of resistive defects is carried out considering different power supply voltages. In more detail, the behavior of defective cells operating under different power supply voltages has been investigated performing SPICE simulations. Results show that the power supply voltage plays an important role in the faulty behavior of both CMOS- and FinFET-based SRAM cells in the presence of resistive defects but demonstrate to be more expressive when considering the FinFET-based memories. Studying different operating temperatures, the results show an expressively higher occurrence of dynamic faults in FinFET-based SRAMs when compared to CMOS technology.

中文翻译：

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比较存在电阻缺陷时电源电压对基于 CMOS 和 FinFET 的 SRAM 的影响

由于工艺变化 (PV)、漏电流增加、随机掺杂波动 (RDF) 以及主要是短沟道效应 (SCE) 等多种因素，CMOS 技术缩放在 22 纳米技术节点上已达到极限。为了在保持系统可靠性和性能的同时通过技术缩小来继续小型化过程，鳍式场效应晶体管 (FinFET) 出现作为 CMOS 晶体管的替代品。与此同时，静态随机存取存储器 (SRAM) 越来越多地占据片上系统 (SoC) 硅面积的很大一部分，这使得它们的可靠性成为一个重要问题。SRAM 旨在达到制造工艺极限的密度，使该组件容易受到制造缺陷的影响，包括电阻缺陷。这种缺陷可能会在电路的使用寿命期间导致动态故障，试逃的一个重要原因。因此，考虑到不同的操作条件来识别正确的故障行为被认为是保证开发更合适的测试方法的关键。在这种情况下，考虑到不同的电源电压，在存在电阻缺陷的情况下，对基于 22 nm CMOS 和基于 20 nm FinFET 的 SRAM 的行为进行了比较。更详细地，已经通过执行 SPICE 仿真研究了在不同电源电压下运行的有缺陷单元的行为。结果表明，在存在电阻缺陷的情况下，电源电压在基于 CMOS 和基于 FinFET 的 SRAM 单元的故障行为中起着重要作用，但在考虑基于 FinFET 的存储器时表现出更强的表现力。