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Comparing the Impact of Power Supply Voltage on CMOS- and FinFET-Based SRAMs in the Presence of Resistive Defects

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Abstract

CMOS technology scaling has reached its limit at the 22 nm technology node due to several factors including Process Variations (PV), increased leakage current, Random Dopant Fluctuation (RDF), and mainly the Short-Channel Effect (SCE). In order to continue the miniaturization process via technology down-scaling while preserving system reliability and performance, Fin Field-Effect Transistors (FinFETs) arise as an alternative to CMOS transistors. In parallel, Static Random-Access Memories (SRAMs) increasingly occupy great part of Systems-on-Chips’ (SoCs) silicon area, making their reliability an important issue. SRAMs are designed to reach densities at the limit of the manufacturing process, making this component susceptible to manufacturing defects, including the resistive ones. Such defects may cause dynamic faults during the circuits’ lifetime, an important cause of test escape. Thus, the identification of the proper faulty behavior taking different operating conditions into account is considered crucial to guarantee the development of more suitable test methodologies. In this context, a comparison between the behavior of a 22 nm CMOS-based and a 20 nm FinFET-based SRAM in the presence of resistive defects is carried out considering different power supply voltages. In more detail, the behavior of defective cells operating under different power supply voltages has been investigated performing SPICE simulations. Results show that the power supply voltage plays an important role in the faulty behavior of both CMOS- and FinFET-based SRAM cells in the presence of resistive defects but demonstrate to be more expressive when considering the FinFET-based memories. Studying different operating temperatures, the results show an expressively higher occurrence of dynamic faults in FinFET-based SRAMs when compared to CMOS technology.

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References

  1. Adams RD, Cooley ES (1996) Analysis of a deceptive destructive read memory fault model and recommended testing. In Proc. IEEE North Atlantic Test Workshop

  2. Bhattacharya D, Jha NK (2014) FinFETs: from devices to architectures. Adv Electron 2014:1–21

    Article  Google Scholar 

  3. Bhoj AN, Simsir MO, Jha NK (2012) Fault models for logic circuits in the multigate era. IEEE Trans Nanotechnol 11(1):182–193

    Article  Google Scholar 

  4. Borri S, Hage-Hassan M, Dilillo L, Girard P, Pravossoudovitch S, Virazel A (2005) Analysis of dynamic faults in embedded-SRAMs: implications for memory test. J Electron Test 21(2):169–179

    Article  Google Scholar 

  5. Bosio A, Dilillo L, Girard P, Pravossoudovitch S, Virazel A (2012) Advanced test methods for SRAMs. In Proc. 2012 IEEE 30th VLSI Test Symposium (VTS), 300–301

  6. Burenkov A, Lorenz J (2002) Three-dimensional simulation of the channel stop implant effects in sub-quarter micron PMOS transistors. In Proc. 32nd European Solid-State Device Research Conference, 339–342

  7. Burnett D, Parihar S, Ramamurthy H, Balasubramanian S (2014) FinFET SRAM design challenges. In Proc. 2014 IEEE International Conference on IC Design & Technology, no. 512, 6–9

  8. Champac V, Vázquez Hernández J, Barceló S, Gomez R, Hawkins C, Segura J (2012) Testing of stuck-open faults in nanometer technologies. IEEE Des Test Comput 29(4):80–91

    Article  Google Scholar 

  9. Copetti TS, Medeiros GC, Poehls LMB, Balen TR (2017) Analyzing the behavior of FinFET SRAMs with resistive defects. In Proc. 2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 1–6

  10. Copetti TS, Balen TR, Brum E, Aquistapace C, Poehls LB (2019) A comparative study between FinFET and CMOS-based SRAMs under resistive defects. In Proc. 2019 IEEE Latin American Test Symposium (LATS), 1-6

  11. de Goor AJ (1991) Testing semiconductor memories: theory and practice. J. Wiley & Sons

  12. Deshmukh R, Khanzode A, Kakde S, Shah N (2015) Compairing FinFETs: SOI Vs bulk: process variability, process cost, and device performance. In Proc. 2015 International Conference on Computer, Communication and Control (IC4), 1–4

  13. Dilillo L, Girard P, Pravossoudovitch S, Virazel A, Borri S, Hage-Hassan M (2004) Resistive-open defects in embedded-SRAM core cells: analysis and march test solution. In Proc. 13th Asian Test Symposium, 266–271

  14. Dilillo L, Girard P, Pravossoudovitch S, Virazel A, Borri S, Hage-Hassan M (2004) Dynamic read destructive fault in embedded-SRAMs: Analysis and march test solution. In Proc. ETS: European Test Symposium, 140–145

  15. Farkhani H, Peiravi A, Kargaard JM, Moradi F (2014) Comparative study of FinFETs versus 22nm bulk CMOS technologies: SRAM design perspective. In Proc. IEEE International System on Chip Conference, 449–454

  16. Fonseca RA et al (2010) Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes. In Proc. 2010 15th IEEE European Test Symposium, 132–137

  17. Hamdioui S, Al-Ars Z, Van De Goor AJ (2002) Testing static and dynamic faults in random access memories. In Proc. 20th IEEE VLSI Test Symposium (VTS 2002), 395–400

  18. Harutyunyan G, Tshagharyan G, Vardanian V, Zorian Y (2014) Fault modeling and test algorithm creation strategy for FinFET-based memories. In Proc. IEEE VLSI Test Symposium

  19. Harutyunyan G, Tshagharyan G, Zorian Y (2015) Test and repair methodology for FinFET-based memories. IEEE Trans Device Mater Reliab 15(1):3–9

    Article  Google Scholar 

  20. Heinig A et al (2014) System integration -The bridge between More than Moore and More Moore. In Proc. 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1–9

  21. Huang X et al (1999) Sub 50-nm FinFET: PMOS. In Proc. International Electron Devices Meeting 1999. Technical Digest (Cat. No. 99CH36318), 67–70

  22. Lin CW, Chao MCT, Hsu CC (2013) Investigation of gate oxide short in FinFETs and the test methods for FinFET SRAMs. In Proc. IEEE VLSI Test Symposium, 0–5

  23. Liu Y, Xu Q (2012) On modeling faults in FinFET logic circuits. In Proc. IEEE International Test Conference, 1–9

  24. Medeiros G, Brum E, Poehls LB, Copetti T, Balen T (2018) Influence of temperature on dynamic fault behavior due to resistive defects in FinFET-based SRAMs. In Proc. 2018 IEEE 19th Latin-American Test Symposium (LATS), 1–6

  25. Medeiros GC, Brum E, Poehls LB, Copetti T, Balen T (2019) Evaluating the impact of temperature on dynamic fault behaviour of FinFET-based SRAMs with resistive defects. J Electron Test 35(2):191–200

    Article  Google Scholar 

  26. Mesalles F, Villacorta H, Renovell M, Champac V (2016) Behavior and test of open-gate defects in FinFET based cells. In Proc. 21th IEEE European Test Symposium (ETS), 1–6

  27. Nanoscale Integration and Modeling (NIMO) (2012) Predictive Technology Model (PTM) [Online]. Available: http://ptm.asu.edu/

  28. Needham W, Prunty C, Yeoh EH (1998) High volume microprocessor test escapes, an analysis of defects our tests are missing. In Proc. International Test Conference 1998 (IEEE Cat. No. 98CH36270), 25–34

  29. Roy K, Jung B, Peroulis D, Raghunathan A (2013) Integrated systems in the more-than-moore era: designing low-cost energy-efficient systems using heterogeneous components. IEEE Des Test 33(3):56–65

    Article  Google Scholar 

  30. Simsir MO, Bhoj A, Jha NK (2010) Fault modeling for FinFET circuits. In Proc. 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 41–46

  31. van de Goor AJ, Al-Ars Z (2000) Functional memory faults: a formal notation and a taxonomy. In Proc. 18th IEEE VLSI Test Symposium, 281–289

  32. van de Goor AJ, Gaydadjiev GN, Mikitjuk VG, Yarmolik VN (1996) March LR: a test for realistic linked faults. In Proc. of 14th VLSI Test Symposium, 272–280

  33. Vazquez J, Champac V, Hawkins C, Segura J (2009) Stuck-open fault leakage and testing in nanometer technologies. In Proc. IEEE VLSI Test Symposium, 315–320

  34. Villacorta H, Segura J, Champac V (2016) Impact of fin-height on SRAM soft error sensitivity and cell stability. J Electron Test 32(3):307–314

    Article  Google Scholar 

  35. Von Arnim K et al (2007) A low-power Multi-Gate FET CMOS technology with 13.9ps inverter delay, large-scale integrated high performance digital circuits and SRAM. In Proc. 2007 IEEE Symposium on VLSI Technology, 106–107

  36. Wilson L (2013) International technology roadmap for semiconductors (ITRS). Semicond. Ind. Assoc

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Correspondence to L. Bolzani Poehls.

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Copetti, T., Balen, T.R., Brum, E. et al. Comparing the Impact of Power Supply Voltage on CMOS- and FinFET-Based SRAMs in the Presence of Resistive Defects. J Electron Test 36, 271–284 (2020). https://doi.org/10.1007/s10836-020-05869-2

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