This article presents the low-power ternary arithmetic logic unit (ALU) design in carbon nanotube field-effect transistor (CNFET) technology. CNFET unique characteristic of geometry-dependent threshold voltage is employed in the multi-valued logic design. The ternary logic benefit of reduced circuit overhead is exploited by embedding multiple modules within a block. The existence of symmetric literals among various single shift and dual shift operators in addition and subtraction operations results in the optimized realization of adder/subtractor modules. The proposed design is based on the notion of multiplexing either arithmetic, logical or miscellaneous operations, depending upon the status of input selection trits. The results obtained by the synopsis HSPICE simulator with the Stanford 32 nm CNFET technology illustrate that the proposed processing modules outperform their counterparts in terms of power consumption, energy consumption and device count. The proposed methodology leads to saving in power consumption and energy consumption (PDP) of 62% and 58%, respectively, on the benchmark circuit of the ALU [full adder/subtractor (FAS)]. Furthermore, for the 2-trit multiplier design, the enhanced performance at the architecture and circuit level is achieved through the optimized designs of various adder and multiplier circuits.

中文翻译：

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CNTFET 技术中的节能三元算术逻辑单元设计

本文介绍了碳纳米管场效应晶体管 (CNFET) 技术中的低功耗三元算术逻辑单元 (ALU) 设计。在多值逻辑设计中采用了 CNFET 独特的几何相关阈值电压特性。通过在一个块中嵌入多个模块，可以利用减少电路开销的三元逻辑优势。加法和减法运算中各种单移位和双移位运算符之间对称文字的存在导致加法器/减法器模块的优化实现。建议的设计基于多路复用算术、逻辑或杂项运算的概念，具体取决于输入选择 Trit 的状态。使用斯坦福 32 nm CNFET 技术的概要 HSPICE 模拟器获得的结果表明，所提出的处理模块在功耗、能耗和设备数量方面优于同类产品。所提出的方法在 ALU [全加法器/减法器 (FAS)] 的基准电路上分别节省了 62% 和 58% 的功耗和能耗 (PDP)。此外，对于2-trit乘法器设计，通过各种加法器和乘法器电路的优化设计，实现了架构和电路级别的增强性能。在 ALU [全加器/减法器 (FAS)] 的基准电路上。此外，对于2-trit乘法器设计，通过各种加法器和乘法器电路的优化设计，实现了架构和电路级别的增强性能。在 ALU [全加器/减法器 (FAS)] 的基准电路上。此外，对于2-trit乘法器设计，通过各种加法器和乘法器电路的优化设计，实现了架构和电路级别的增强性能。