This communication presents the performance analysis and impact of low frequency flicker noise on a dual dielectric pocket heterojunction silicon on insulator (SOI) tunnel FET (TFET). The proposed TFET structure is well optimized for different gate-source underlap length and various thickness of δp⁺ Si_1-xGe_x layer. It offers an ON current of 1.16 × 10⁻⁴ A/μm providing a high ON/OFF ratio of 3.49 × 10¹² and a super steeper sub-threshold swing of 2 mV/dec. The device performance is investigated with concern to interface traps while both Uniform and Gaussian trap distributions are considered. The analyses specify that the proposed device is insusceptible to ON current degradation in presence of interface traps in comparison to OFF current behaviour. Electrical noise performance is examined in presence of interface traps and different mole fraction of germanium (Ge) in δp⁺ Si_1-xGe_x layer. The device is further tested for its parasitic capacitances and transconductance to drain current ratio (g_m/I_D) behaviour. The high ratio of obtained g_m/I_D makes it compatible for future low power applications.

此通信介绍了性能分析以及低频闪烁噪声对绝缘体上双电介质口袋异质结硅（SOI）隧道FET（TFET）的影响。所提出的TFET结构针对不同的栅极-源极重叠长度和不同的δp ⁺ Si _1-x Ge _x层厚度进行了优化。它提供1.16×10 ^-4 A /μm的导通电流，提供3.49×10 ¹²的高导通/截止比以及2mV / dec的超陡峭亚阈值摆幅。在考虑均匀陷阱分布和高斯陷阱分布的同时，研究了与接口陷阱有关的器件性能。分析表明，与关断电流行为相比，所提出的器件在存在界面陷阱的情况下不容易受到导通电流下降的影响。在存在界面陷阱和δp ⁺ Si _1-x Ge _x层中锗（Ge）不同摩尔分数的情况下，检查了电噪声性能。对该器件的寄生电容和跨导漏电流比（g _m / I _D）行为进行了进一步测试。获得的高比g _m / I _D 使它与未来的低功耗应用兼容。