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A Study on Dual Dielectric Pocket Heterojunction SOI Tunnel FET Performance and Flicker Noise Analysis in Presence of Interface Traps

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Abstract

This communication presents the performance analysis and impact of low frequency flicker noise on a dual dielectric pocket heterojunction silicon on insulator (SOI) tunnel FET (TFET). The proposed TFET structure is well optimized for different gate-source underlap length and various thickness of δp+ Si1-xGex layer. It offers an ON current of 1.16 × 10−4 A/μm providing a high ON/OFF ratio of 3.49 × 1012 and a super steeper sub-threshold swing of 2 mV/dec. The device performance is investigated with concern to interface traps while both Uniform and Gaussian trap distributions are considered. The analyses specify that the proposed device is insusceptible to ON current degradation in presence of interface traps in comparison to OFF current behaviour. Electrical noise performance is examined in presence of interface traps and different mole fraction of germanium (Ge) in δp+ Si1-xGex layer. The device is further tested for its parasitic capacitances and transconductance to drain current ratio (gm/ID) behaviour. The high ratio of obtained gm/ID makes it compatible for future low power applications.

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Authors and Affiliations

  1. ECE Department, NIT Silchar, Silchar, Assam, India

    Debika Das & Ujjal Chakraborty

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  1. Debika Das
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  2. Ujjal Chakraborty
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Correspondence to Debika Das.

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Das, D., Chakraborty, U. A Study on Dual Dielectric Pocket Heterojunction SOI Tunnel FET Performance and Flicker Noise Analysis in Presence of Interface Traps. Silicon 13, 787–798 (2021). https://doi.org/10.1007/s12633-020-00488-0

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  • DOI: https://doi.org/10.1007/s12633-020-00488-0

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