A new technique called series-connected dynamic node-driven transistor domino logic (SCDNDTDL) is proposed for the design of circuits with high speed and low power consumption in fin-shaped field-effect transistor (FinFET) technology. HSPICE is used to simulate 2-, 4-, 8-, and 16-input domino OR gates in complementary metal–oxide–semiconductor (CMOS) and FinFET technology using the 32-nm Predictive Technology Model (PTM) library with a supply voltage of 0.9 V. The proposed technique shows a maximum power reduction of 73.16% in the FinFET short gate (SG) mode as compared with the conditional stacked keeper domino logic (CSK-DL) technique and a maximum delay reduction of 36.36% in the FinFET SG mode as compared with the voltage comparison-based domino (VCD) technique at a frequency of 50 MHz. The unity noise gain of the proposed circuit is 1.64 to 3.77 times higher in the FinFET SG mode and 1.39 to 3.77 times higher in the FinFET low-power (LP) mode compared with different existing techniques. The proposed circuit has up to 18.94 times higher figure of merit (FOM) in the SG mode and up to 7.14 times higher FOM in the LP mode compared with existing techniques. The proposed circuit in FinFET technology shows a maximum power reduction of 68.47% as compared with its counterpart in CMOS technology for a 16-input OR gate. The proposed circuit has 6.06 times lower energy–delay product and 4.53 times lower power–delay product compared with its counterpart in CMOS technology for a 16-input OR gate.

中文翻译：

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SCDNDTDL：FinFET技术中用于设计低功耗多米诺骨牌电路的技术

针对鳍形场效应晶体管（FinFET）技术中的高速低功耗电路设计，提出了一种称为串联动态节点驱动晶体管多米诺逻辑（SCDNDTDL）的新技术。HSPICE用于在互补金属氧化物半导体（CMOS）和FinFET技术中使用32-nm预测技术模型（PTM）库来模拟2、4、8和16输入的多米诺或门为0.9V。所提出的技术与条件堆叠式保持器多米诺逻辑（CSK-DL）技术相比，在FinFET短栅极（SG）模式下显示的最大功耗降低了73.16％，而FinFET中的最大延迟降低了36.36％ SG模式与基于电压比较的多米诺骨牌（VCD）技术在50 MHz频率下的比较。拟议电路的单位噪声增益为1.64至3。与现有技术不同，FinFET SG模式下的功耗高77倍，FinFET低功耗（LP）模式下的功耗高1.39至3.77倍。与现有技术相比，拟议的电路在SG模式下具有高达18.94倍的品质因数（FOM），在LP模式下具有高达7.14倍的FOM。FinFET技术中建议的电路与16输入或门的CMOS技术相比，其最大功耗降低了68.47％。与采用CMOS技术的16输入或门相比，该电路的能量延迟乘积低6.06倍，功率延迟乘积低4.53倍。与现有技术相比，SG模式下的品质因数（FOM）高94倍，LP模式下的FOM高达7.14倍。FinFET技术中建议的电路与16输入或门的CMOS技术相比，其最大功耗降低了68.47％。与采用CMOS技术的16输入或门相比，该电路的能量延迟乘积低6.06倍，功率延迟乘积低4.53倍。与现有技术相比，SG模式下的品质因数（FOM）高94倍，LP模式下的FOM高达7.14倍。FinFET技术中建议的电路与16输入或门的CMOS技术相比，其最大功耗降低了68.47％。与采用CMOS技术的16输入或门相比，该电路的能量延迟乘积低6.06倍，功率延迟乘积低4.53倍。