Since the early nineties the lack of scalability of fitness evaluation has been the main bottleneck preventing the adoption of evolutionary algorithms for logic circuits synthesis. Recently, various formal approaches such as SAT and BDD solvers have been introduced to this field to overcome this issue. This made it possible to optimise complex circuits consisting of hundreds of inputs and thousands of gates. Unfortunately, we are facing another problem—scalability of representation. The efficiency of the evolutionary optimization applied at the global level deteriorates with the increasing complexity. To overcome this issue, we propose to apply the concept of local resynthesis in this work. Local resynthesis is an iterative process based on the extraction of smaller sub-circuits from a complex circuit that are optimized locally and implanted back to the original circuit. When applied appropriately, this approach can mitigate the problem of scalability of representation. Two complementary approaches to the extraction of the sub-circuits are presented and evaluated in this work. The evaluation is done on a set of highly optimized complex benchmark problems representing various real-world controllers, logic and arithmetic circuits. The experimental results show that the evolutionary resynthesis provides better results compared to globally operating evolutionary optimization. In more than 85% cases, a substantially higher number of redundant gates was removed while keeping the computational effort at the same level. A huge improvement was achieved especially for the arithmetic circuits. On average, the proposed method was able to remove 25.1% more gates.

中文翻译：

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基于 EA 的再综合：优化数字电路的有效工具

自 90 年代初以来，适应度评估缺乏可扩展性一直是阻碍采用进化算法进行逻辑电路综合的主要瓶颈。最近，该领域引入了各种形式化方法，例如 SAT 和 BDD 求解器，以解决这个问题。这使得优化由数百个输入和数千个门组成的复杂电路成为可能。不幸的是，我们正面临另一个问题——表示的可扩展性。在全局层面应用的进化优化的效率随着复杂性的增加而恶化。为了克服这个问题，我们建议在这项工作中应用局部再合成的概念。局部再合成是一个迭代过程，它基于从复杂电路中提取较小的子电路，这些子电路在本地优化并植入到原始电路中。如果应用得当，这种方法可以缓解表示的可扩展性问题。在这项工作中提出并评估了两种提取子电路的互补方法。评估是在一组高度优化的复杂基准问题上完成的，这些问题代表各种真实世界的控制器、逻辑和算术电路。实验结果表明，与全局操作进化优化相比，进化再合成提供了更好的结果。在超过 85% 的情况下，移除了大量冗余门，同时将计算工作量保持在同一水平。特别是在算术电路方面取得了巨大的进步。平均而言，所提出的方法能够多移除 25.1% 的门。