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EA-based resynthesis: an efficient tool for optimization of digital circuits

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Abstract

Since the early nineties the lack of scalability of fitness evaluation has been the main bottleneck preventing the adoption of evolutionary algorithms for logic circuits synthesis. Recently, various formal approaches such as SAT and BDD solvers have been introduced to this field to overcome this issue. This made it possible to optimise complex circuits consisting of hundreds of inputs and thousands of gates. Unfortunately, we are facing another problem—scalability of representation. The efficiency of the evolutionary optimization applied at the global level deteriorates with the increasing complexity. To overcome this issue, we propose to apply the concept of local resynthesis in this work. Local resynthesis is an iterative process based on the extraction of smaller sub-circuits from a complex circuit that are optimized locally and implanted back to the original circuit. When applied appropriately, this approach can mitigate the problem of scalability of representation. Two complementary approaches to the extraction of the sub-circuits are presented and evaluated in this work. The evaluation is done on a set of highly optimized complex benchmark problems representing various real-world controllers, logic and arithmetic circuits. The experimental results show that the evolutionary resynthesis provides better results compared to globally operating evolutionary optimization. In more than 85% cases, a substantially higher number of redundant gates was removed while keeping the computational effort at the same level. A huge improvement was achieved especially for the arithmetic circuits. On average, the proposed method was able to remove 25.1% more gates.

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Notes

  1. The window of a Boolean network N is a connected subnetwork \(N'\subseteq N\) that corresponds to the subset of nodes of the network containing nodes from root set together with all nodes on paths between the leaf set and the root set. The nodes in the leaf set are not included in the window.

  2. The Verilog netlists of the benchmark circuits are taken from https://lsi.epfl.ch/MIG.

  3. The following circuits were used to determine the best parameter setting: dsp, mem_ctrl, tv80, diffeq1, max, revx.

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Authors and Affiliations

  1. Faculty of Information Technology, Brno University of Technology, IT4Innovations Centre of Excellence, Brno, Czech Republic

    Jitka Kocnova & Zdenek Vasicek

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  1. Jitka Kocnova
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  2. Zdenek Vasicek
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Correspondence to Zdenek Vasicek.

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This work was supported by Czech Science Foundation Project 19-10137S.

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Kocnova, J., Vasicek, Z. EA-based resynthesis: an efficient tool for optimization of digital circuits. Genet Program Evolvable Mach 21, 287–319 (2020). https://doi.org/10.1007/s10710-020-09376-3

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