Abstract A dual side doping-less (DL) GaAs0.5Sb0·5/In0.53Ga0.47As heterojunction tunnel FET (DDL-HTFET) configuration together with hetero-gate-dielectric material (HfO2/SiO2) has been proposed in this article. Hence, N+-pocket with varying electron concentration has been implemented by changing the length of source-side channel (LSC) beneath the gate. The impact of interface trap charges (ITCs) on the execution of the proposed device has been examined by initiating dual (donor and acceptor) sort of confined charges near the semiconductor/insulator intersection. An assessment has been carried out among proposed HTFET and Si-based devices having similar dimensions with respect to dc, analog/RF, and linearity distortion factors thoroughly in existence of ITCs. ATLAS simulations illustrate that the proposed DDL-HTFET is more protected in terms of performance deviation than its Si-based contenders with various ITCs existing at semiconductor/insulator intersection. Hence, DDL-HTFET model can be a promising candidate for the low-power RF applications and can offer improved linearity and less distortion.

中文翻译：

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GaAs0.5Sb0.5/ In0.53Ga0.47As 异质结无掺杂电荷等离子体基隧道 FET，用于提高模拟/数字性能

摘要 本文提出了一种双侧无掺杂 (DL) GaAs0.5Sb0·5/In0.53Ga0.47As 异质结隧道 FET (DDL-HTFET) 配置以及异质栅介质材料 (HfO2/SiO2)。因此，通过改变栅极下方源极侧沟道 (LSC) 的长度，已经实现了具有不同电子浓度的 N+-pocket。通过在半导体/绝缘体交叉点附近启动双（施主和受主）类型的受限电荷，已经检查了界面陷阱电荷 (ITC) 对所提出设备的执行的影响。在存在 ITC 的情况下，已经对建议的 HTFET 和基于硅的器件进行了评估，这些器件在直流、模拟/RF 和线性失真因素方面具有相似的尺寸。ATLAS 模拟表明，在性能偏差方面，所提出的 DDL-HTFET 比其基于硅的竞争者在半导体/绝缘体交叉处存在各种 ITC 时受到更多保护。因此，DDL-HTFET 模型可以成为低功率 RF 应用的有希望的候选者，并且可以提供更好的线性度和更少的失真。