GaAs_0.5Sb_0.5/ In_0.53Ga_0.47As heterojunction dopingless charge plasma-based tunnel FET for analog/digital performance improvement

Highlights

• GaAs_0.5Sb_0·5/In_0.53Ga_0.47 TFET offers enhanced I_ON, suppress ambipolar current, and increase RF/Analog performance.

• Proposed TFET has a higher I_ON and a steeper SS.

• Proposed model achieves improved linearity and lesser distortion compared to other existing structures.

Abstract

A dual side doping-less (DL) GaAs_0.5Sb_0·5/In_0.53Ga_0.47As heterojunction tunnel FET (DDL-HTFET) configuration together with hetero-gate-dielectric material (HfO₂/SiO₂) has been proposed in this article. Hence, N⁺-pocket with varying electron concentration has been implemented by changing the length of source-side channel (L_SC) beneath the gate. The impact of interface trap charges (ITCs) on the execution of the proposed device has been examined by initiating dual (donor and acceptor) sort of confined charges near the semiconductor/insulator intersection. An assessment has been carried out among proposed HTFET and Si-based devices having similar dimensions with respect to dc, analog/RF, and linearity distortion factors thoroughly in existence of ITCs. ATLAS simulations illustrate that the proposed DDL-HTFET is more protected in terms of performance deviation than its Si-based contenders with various ITCs existing at semiconductor/insulator intersection. Hence, DDL-HTFET model can be a promising candidate for the low-power RF applications and can offer improved linearity and less distortion.

Introduction

With latest development in the area of MOS technology, device dimensions are miniaturized to nanometer range [1]. Greater sub threshold swing (SS) (nearly higher than 60 mV/decade at room temperature) and high leakage current [2,3] have been reported as serious concerns for scaled devices. TFET has gained significant attention by surmounting these limitations. Owing to BTBT mechanisms for conduction purpose, TFET comprises less SS and reduced OFF-state current (I_OFF) but lower I_ON and inferior ambipolar nature [4,5]. Plethora of TFET structures has been reported in literature to overcome the limitations. Mainly, the work function engineering [[6], [7], [8]], band-gap engineering [6,9], gate dielectric engineering [9,10], Core-shell architecture [11,12] and electrostatically doped (ED) gate underlap structure [13] are the most significant ones. Recently, the doping-less (DL) architecture has drawn enormous interest. Depending on the DL perception [12,14,15], P⁺ type (N⁺ type) source (drain) sections in a TFET can be implemented by the metal having suitable work function connecting with the semiconductor. In addition, DL-TFET suppresses the difficulties of RDF [16] and provides protection against sensitivity to parameter deviation [17]. Although, Si-based DL-TFET reveals a low I_ON due to huge electronic tunneling mass for silicon as well as poor lateral-electric field inside the tunneling zone, identical concerning to traditional Si-based TFET [14,15]. Table 1 presents the assessment of recent state-of-the-art silicon-based TFET devices [[6], [7], [8], [9], [10], [11], [12], [13]] with the proposed model, i.e., GaAs_0.5Sb_0·5/In_0.53Ga_0.47As DDL-HTFET together with HfO₂/SiO₂ hetero-gate-dielectric material. Hence the proposed device excels the other TFET contenders. Analogous to the charge plasma perception, the identical metal work-function (φ_M) introduced at GaAs_0.5Sb_0.5 and In_0.53Ga_0.47As can outcome in dissimilar electron concentrations in their relevant portions. This is due to various energy-gaps and electron affinities in two separate materials [[18], [19], [20]] as described in Table 2. Here, the N⁺-pocket can be introduced within the source-side channel (SSC) regime beneath the gate by selecting the proper φ_M; provided, the width as well as the electron concentration of the N⁺-pocket are varying with the L_SC. Moreover, N⁺-pocket formation in DL-TFET can be achieved without incorporating ion implantation or the dual-material gate [21], hence offers easier fabrication process and low thermal budgeting [22].

Moreover, through implementation of devices in nanometer range, the existence of interface trap charges (ITCs) induced by entrapping of mobile ions along with fixed oxide charges near the semiconductor/insulator intersection generates reliability concerns upon the device execution [23,24]. Hence, we have carried out a thorough examination of the impact of ITCs on proposed DDL-HTFET and Si-based devices respecting dc, analog/RF performance, and linearity distortion factors. The trap oxide charges generally arise owing to induced damages by stress as well as process throughout fabrication procedure, which can degrade the execution of the device with respect to reliability issues [25,26]. An acceptor (donor) IT can act similar to negative (positive) confined charge i.e. loaded (vacant) with electrons or neutral confined charge i.e. vacant (loaded) with electron. In reality, acceptor (donor) traps stay beneath (over) the conduction (valence) energy level. In TFETs, the ITs mostly occur owing to high lateral electric field (E_x) accessible near the tunneling interface. Besides elevated E_x, generation of ITC occurs owing to hot-carrier stress (HCS) along with positive bias temperature instability (PBTI) [[23], [24], [25]]. The band to band tunneling (BTBT) rate is comparative to exp (-A/E_x) ⁶, thus BTBT rate is extremely sensitive to E_x. However the existence of ITCs near the semiconductor/insulator intersection consequences into deterioration of E_x along the length of channel region near the tunneling intersection and hence tunneling current reduces and also device performance deteriorates. Hence, it is extremely essential to recognize the reliability of TFET with various ITCs.

GaAs_0.5Sb_0·5/In_0.53Ga_0.47As, type II super-lattices (SL) are interesting materials for short-wave infrared (SWIR), mid-wave infrared (MWIR) Photo-detectors (PD) and light-emitting diodes (LEDs), particularly for the SWIR recognitions varying from 1 to 2.5 μm [20]. Hetero-junction based on GaAs_0.5Sb_0·5/In_0.53Ga_0.47As can be a promising structure due to its lattice matching with InP substrate [19,27], which can extensively enhance I_ON by diminishing the tunneling barrier. Moreover, the HfO₂/SiO₂ hetero-gate-dielectric is employed in the DDL-HTFET to enhance the device efficiency. Hence, HfO₂ offers higher electric field for achieving enhanced I_ON, and SiO₂ can evade rising the ambipolar current. This article is arranged as follows. Section 2 deals with the structural description and simulation setup. The assessments of device performances between the proposed-TFET and Si-based structures are investigated in Section 3 elaborately. Finally, Section 4 concludes the paper.