Normalization and envelope generation of signals are essential pre-processing steps in many signal processing applications. With the emergence of high-performance computing and the need for hardware accelerators in digital signal processing, research for hardware efficient solutions has become a necessity. Interpolation and signal normalization algorithms, though have been implemented in software systems extensively, however, lack the research in hardware system solutions. In this paper, an envelope-based signal normalization technique has been presented along with a detailed discussion on the usage of cubic hermite interpolation. The hardware accelerator architecture for cubic hermite interpolation is presented, and the same is implemented on a field-programmable gate array (FPGA). It is found that the envelope method of normalization which uses interpolation performs better in terms of speed, hardware re-usability and complexity. Using cubic hermite interpolation, an architecture for hardware accelerator for the signal normalization is implemented on FPGA. The hardware accelerator is tested using data obtained from frequency-modulated continuous wave radar. The MATLAB simulation results for both interpolation and normalization are compared with the FPGA implementation results of the same. An average root mean square error and correlation of $$1.67 \times 10^{-4}$$ 1.67 × 10 - 4 and 99.78% for interpolation and $$2.1 \times 10^{-4}$$ 2.1 × 10 - 4 and 99.71% for normalization are obtained.

中文翻译：

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一种用于信号归一化的新型高效硬件加速器架构

信号的归一化和包络生成是许多信号处理应用中必不可少的预处理步骤。随着高性能计算的出现以及数字信号处理中对硬件加速器的需求，研究硬件高效的解决方案已成为必要。插值和信号归一化算法虽然已经在软件系统中广泛实现，但缺乏对硬件系统解决方案的研究。在本文中，提出了一种基于包络的信号归一化技术，并详细讨论了三次厄米插值的用法。介绍了三次厄米插值的硬件加速器架构，并在现场可编程门阵列 (FPGA) 上实现了相同的架构。发现使用插值的归一化包络方法在速度、硬件可重用性和复杂度方面表现更好。使用三次厄米插值，在FPGA上实现了用于信号归一化的硬件加速器架构。硬件加速器使用从调频连续波雷达获得的数据进行测试。将插值和归一化的 MATLAB 仿真结果与相同的 FPGA 实现结果进行比较。平均均方根误差和相关性 $$1.67 \times 10^{-4}$$ 1.67 × 10 - 4 和 99.78% 插值和 $$2.1 \times 10^{-4}$$ 2.1 × 10 - 4 和获得了 99.71% 的归一化率。用于信号归一化的硬件加速器架构在 FPGA 上实现。硬件加速器使用从调频连续波雷达获得的数据进行测试。将插值和归一化的 MATLAB 仿真结果与相同的 FPGA 实现结果进行比较。平均均方根误差和相关性 $$1.67 \times 10^{-4}$$ 1.67 × 10 - 4 和 99.78% 插值和 $$2.1 \times 10^{-4}$$ 2.1 × 10 - 4 和获得了 99.71% 的归一化率。用于信号归一化的硬件加速器架构在 FPGA 上实现。硬件加速器使用从调频连续波雷达获得的数据进行测试。将插值和归一化的 MATLAB 仿真结果与相同的 FPGA 实现结果进行比较。平均均方根误差和相关性 $$1.67 \times 10^{-4}$$ 1.67 × 10 - 4 和 99.78% 插值和 $$2.1 \times 10^{-4}$$ 2.1 × 10 - 4 和获得了 99.71% 的归一化率。