Abstract
Normalization and envelope generation of signals are essential pre-processing steps in many signal processing applications. With the emergence of high-performance computing and the need for hardware accelerators in digital signal processing, research for hardware efficient solutions has become a necessity. Interpolation and signal normalization algorithms, though have been implemented in software systems extensively, however, lack the research in hardware system solutions. In this paper, an envelope-based signal normalization technique has been presented along with a detailed discussion on the usage of cubic hermite interpolation. The hardware accelerator architecture for cubic hermite interpolation is presented, and the same is implemented on a field-programmable gate array (FPGA). It is found that the envelope method of normalization which uses interpolation performs better in terms of speed, hardware re-usability and complexity. Using cubic hermite interpolation, an architecture for hardware accelerator for the signal normalization is implemented on FPGA. The hardware accelerator is tested using data obtained from frequency-modulated continuous wave radar. The MATLAB simulation results for both interpolation and normalization are compared with the FPGA implementation results of the same. An average root mean square error and correlation of \(1.67 \times 10^{-4}\) and 99.78% for interpolation and \(2.1 \times 10^{-4}\) and 99.71% for normalization are obtained.
Similar content being viewed by others
References
E. Catmull, R. Rom, A Class of Local Interpolating Splines, Computer Aided Geometric Design (Elsevier, Amsterdam, 1974), pp. 317–326
F.N. Fritsch, R.E. Carlson, Monotone piecewise cubic interpolation. SIAM J. Numer. Anal. 17(2), 238–246 (1980)
G.C. George, A. Moitra, S. Caculo, A.A. Prince, Efficient architecture for implementation of Hermite interpolation on FPGA, in 2018 Conference on Design and Architectures for Signal and Image Processing (DASIP), pp. 7–12 (2018)
G.C. George, A.A. Prince, J.J.U. Buch, S.K. Pathak, Design of configurable multi-mode trigger unit. Measurement 139, 482–489 (2019)
N.E. Huang, Z. Wu, S.R. Long, K.C. Arnold, X. Chen, K. Blank, On instantaneous frequency. Adv. Adapt. Data Anal. 1(2), 177–229 (2009)
R.A. Irizarry, B. Hobbs, F. Collin, Y.D. Beazer-Barclay, K.J. Antonellis et al., Exploration, normalization, and summaries of high density oligonucleotide array probe level data. Biostatistics 4, 249–264 (2003)
L. Jerome, Catmull–Rom curve fitting and interpolation equations. Int. J. Math. Educ. Sci. Technol. 41(6), 842–849 (2010)
V. Kitsakis, K. Nakos, D. Reisis, N. Vlassopoulos, Parallel memory accessing for FFT architectures. J. Signal Process. Syst. 90(11), 1593–1607 (2018)
X. Li, K.N. Plataniotis, A complete color normalization approach to histopathology images using color cues computed from saturation-weighted statistics. IEEE Trans. Biomed. Eng. 62(7), 1862–1873 (2015)
S. Liu, D. Liu, Design space exploration of 1-D FFT processor. J. Signal Process. Syst. 90(11), 1609–1621 (2018)
R. Patel, U. Shrawankar, V.M. Thakare, Normalization techniques for hiding speakers identity, in 2012 International Conference on Data Science & Engineering (ICDSE), pp. 75–80 (2012)
A.A. Prince, V. Kartha, A framework for remote and adaptive partial reconfiguration of SoC based data acquisition systems under Linux, in 10th International Symposium on Reconfigurable and Communication-centric Systems-on-Chip (ReCoSoC), pp. 1–5 (2015)
A.A. Prince, S. Ganesh, P.K. Verma, P. George, D. Raju, Efficient implementation of empirical mode decomposition in FPGA Using Xilinx System Generator, in IECON 2016-42nd Annual Conference of the IEEE Industrial Electronics Society, pp. 895–900 (2016)
T.P. Quinn, T.M. Crowley, M.F. Richardson, Benchmarking differential expression analysis tools for RNA-Seq: normalization-based vs. log-ratio transformation-based methods. BMC Bioinform. 19(1), 274 (2018)
L. Wan, Z. Yang, R. Zhou, X. Pan, C. Zhang et al., Design of Q-band FMCW reflectometry for electron density profile measurement on the Joint TEXT tokamak. Plasma Sci. Technol. 19(2), 025602 (2017)
X. Xiao, E.S. Chng, H. Li, Joint spectral and temporal normalization of features for robust recognition of noisy and reverberated speech, in 2012 IEEE International Conference on Acoustics Speech and Signal Processing (ICASSP), pp. 4325–4328 (2012)
A.R. Yu, J.S. Kim, K.M. Kim, H.J. Kim, Comparison of normalization methods for \({^{124}}{\rm I} \) PET on Siemens Inveon PET Scanner. IEEE Trans. Nucl. Sci. 60, 817–819 (2013)
S. Zhang, B. Chen, L. Yan, X. Zheyi, Real-time normalization and nonlinearity evaluation methods of the PGC-arctan demodulation in an EOM-based sinusoidal phase modulating interferometer. Opt. Express 26(2), 605–616 (2018)
Acknowledgements
This work is funded by the Board of Research in Nuclear Sciences (BRNS), Government of India, with Apl. No. 201806391RP05101-BRNS.
Author information
Authors and Affiliations
Corresponding author
Additional information
Publisher's Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
George, G.C., Moitra, A., Caculo, S. et al. A Novel and Efficient Hardware Accelerator Architecture for Signal Normalization. Circuits Syst Signal Process 39, 2425–2441 (2020). https://doi.org/10.1007/s00034-019-01262-3
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s00034-019-01262-3