Due to the technological advancements, the three dimensional Integrated Circuits become the most popular technology. But it has the major drawback of increased time consumption as well power consumption. This happens because of the increased wire length and routing path for connecting the components in chip. Thus it is essential to reduce the wire length for the purpose of enhancing the circuit speed and minimize the power dissipation. But there may be a chance of temperature rise due to the heat generated by the slacked layers which also needs to be reduced. Several traditional approaches have addressed the issues of temperature rise and layer assignment. But the utilization of through-silicon-via is considered. Thus a new stochastic based genetic algorithm is proposed in this work for reducing the thermal estimations. Also the length of wire can be reduced by determining the minimal path so as to connect the components. Both partitioning and routing process takes place in this approach. The performance of the proposed approach is analyzed using ISPD2008 dataset. Also the results of this stochastic based model are compared with the existing algorithm. The superiority of this proposed approach is proved with reduced wire length and temperature estimations.

由于技术的进步，三维集成电路成为最流行的技术。但是它的主要缺点是增加了时间消耗以及功耗。发生这种情况是由于增加了导线长度和用于连接芯片中组件的布线路径。因此，为了提高电路速度和最小化功耗，必须减小导线长度。但是由于松弛层产生的热量可能会导致温度升高，这也需要减少。几种传统方法已经解决了温度上升和层分配的问题。但是考虑了硅通孔的利用。因此，在这项工作中提出了一种新的基于随机的遗传算法来减少热估计。同样，可以通过确定最小路径以连接部件来减少电线的长度。分区和路由过程都以这种方式进行。使用ISPD2008数据集分析了该方法的性能。还将基于随机模型的结果与现有算法进行比较。减少导线长度和温度估算证明了该方法的优越性。