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Optimization of thermal aware multilevel routing for 3D IC

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Abstract

Due to the technological advancements, the three dimensional Integrated Circuits become the most popular technology. But it has the major drawback of increased time consumption as well power consumption. This happens because of the increased wire length and routing path for connecting the components in chip. Thus it is essential to reduce the wire length for the purpose of enhancing the circuit speed and minimize the power dissipation. But there may be a chance of temperature rise due to the heat generated by the slacked layers which also needs to be reduced. Several traditional approaches have addressed the issues of temperature rise and layer assignment. But the utilization of through-silicon-via is considered. Thus a new stochastic based genetic algorithm is proposed in this work for reducing the thermal estimations. Also the length of wire can be reduced by determining the minimal path so as to connect the components. Both partitioning and routing process takes place in this approach. The performance of the proposed approach is analyzed using ISPD2008 dataset. Also the results of this stochastic based model are compared with the existing algorithm. The superiority of this proposed approach is proved with reduced wire length and temperature estimations.

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Authors and Affiliations

  1. Department of Electronic and Communication Engineering, Kalasalingam Academy of Research and Education, Anand Nagar, Krishnankoil, 626126, India

    P. Sivakumar, K. Pandiaraj & K. JeyaPrakash

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  1. P. Sivakumar
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  2. K. Pandiaraj
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  3. K. JeyaPrakash
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Correspondence to P. Sivakumar.

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Sivakumar, P., Pandiaraj, K. & JeyaPrakash, K. Optimization of thermal aware multilevel routing for 3D IC. Analog Integr Circ Sig Process 103, 131–142 (2020). https://doi.org/10.1007/s10470-019-01513-y

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  • DOI: https://doi.org/10.1007/s10470-019-01513-y

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