Abstract

A successive-approximation-register (SAR) analog-to-digital converter (ADC) topology is presented, which optimizes the time distribution during the conversion. It is based on the semi-synchronous timing and uses a delay-looked loop (DLL) for clock generation. The absence of timing determined by analog delays allows an increase of the conversion speed compared to an asynchronous ADC using the same digital-to-analog converter (DAC), comparator and SAR logic. The results of circuit simulations on transistor level confirm the proper operation of the proposed approach.

中文翻译：

---

使用DLL的具有可变DAC建立时间的半同步SAR ADC

摘要

提出了一种逐次逼近寄存器（SAR）模数转换器（ADC）拓扑，该拓扑可优化转换期间的时间分配。它基于半同步时序，并使用延迟查找循环（​​DLL）来生成时钟。与使用相同的数模转换器（DAC），比较器和SAR逻辑的异步ADC相比，没有由模拟延迟确定的时序，可以提高转换速度。晶体管级电路仿真的结果证实了该方法的正确运行。