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A semi-synchronous SAR ADC with variable DAC settling time using a DLL

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Abstract

A successive-approximation-register (SAR) analog-to-digital converter (ADC) topology is presented, which optimizes the time distribution during the conversion. It is based on the semi-synchronous timing and uses a delay-looked loop (DLL) for clock generation. The absence of timing determined by analog delays allows an increase of the conversion speed compared to an asynchronous ADC using the same digital-to-analog converter (DAC), comparator and SAR logic. The results of circuit simulations on transistor level confirm the proper operation of the proposed approach.

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Authors and Affiliations

  1. Technical University of Sofia, Sofia, Bulgaria

    Georgi Panov & Angel Popov

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  1. Georgi Panov
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  2. Angel Popov
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Correspondence to Georgi Panov.

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Panov, G., Popov, A. A semi-synchronous SAR ADC with variable DAC settling time using a DLL. Analog Integr Circ Sig Process 103, 187–194 (2020). https://doi.org/10.1007/s10470-020-01603-2

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  • DOI: https://doi.org/10.1007/s10470-020-01603-2

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