当前位置: X-MOL 学术J. Real-Time Image Proc. › 论文详情
Our official English website, www.x-mol.net, welcomes your feedback! (Note: you will need to create a separate account there.)
FPGA-accelerated adaptive projection-based image registration
Journal of Real-Time Image Processing ( IF 2.9 ) Pub Date : 2020-03-03 , DOI: 10.1007/s11554-020-00952-5
Pulak Mondal , Swapna Banerjee

In this paper, a high-speed hardware-based image registration is proposed exploiting parallelism and adaptive sampling technique to fulfill the requirement of high-speed portable multimedia devices. This technique computes radial and angular projections in parallel way without converting the image into polar domain, but by adjusting the number of samples along angular direction according to radius length which decreases computational load. Further, a complete image registration algorithm without using any geometric transformation is proposed. The software-based implementation of the proposed algorithm is 1.33 times faster than its latest available method in the literature. The proposed algorithm is mapped in field-programmable gate array (FPGA, Virtex6-xc6vlx760-2-ff1760) and it utilizes \(2.03\%\) Slice LUTs, \(35.14\%\) LUT-FF pair and \(1.27\%\) DSP48E1s; and maximum clock frequency is 266 Mz. The hardware-based implementation of the proposed algorithm is \(10^4\) times faster than software counterpart.



中文翻译:

FPGA加速的基于自适应投影的图像配准

本文提出了一种基于并行硬件和自适应采样技术的高速硬件图像配准技术,以满足高速便携式多媒体设备的需求。该技术以并行方式计算径向投影和角度投影,而无需将图像转换为极性域,而是根据半径长度调整沿角度方向的采样数,从而减少了计算量。此外,提出了一种不使用任何几何变换的完整图像配准算法。该算法的基于软件的实现比文献中最新的方法快1.33倍。将该算法映射到现场可编程门阵列(FPGA,Virtex6-xc6vlx760-2-ff1760)中并利用\(2.03 \%\)切片LUT,\(35.14 \%\) LUT-FF对和\(1.27 \%\) DSP48E1; 最大时钟频率为266 Mz。所提出算法的基于硬件的实现比软件对应的实现快((10 ^ 4 \))倍。

更新日期:2020-03-03
down
wechat
bug