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FPGA-accelerated adaptive projection-based image registration

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Abstract

In this paper, a high-speed hardware-based image registration is proposed exploiting parallelism and adaptive sampling technique to fulfill the requirement of high-speed portable multimedia devices. This technique computes radial and angular projections in parallel way without converting the image into polar domain, but by adjusting the number of samples along angular direction according to radius length which decreases computational load. Further, a complete image registration algorithm without using any geometric transformation is proposed. The software-based implementation of the proposed algorithm is 1.33 times faster than its latest available method in the literature. The proposed algorithm is mapped in field-programmable gate array (FPGA, Virtex6-xc6vlx760-2-ff1760) and it utilizes \(2.03\%\) Slice LUTs, \(35.14\%\) LUT-FF pair and \(1.27\%\) DSP48E1s; and maximum clock frequency is 266 Mz. The hardware-based implementation of the proposed algorithm is \(10^4\) times faster than software counterpart.

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Authors and Affiliations

  1. Institute of Radio Physics and Electronics, Calcutta University, Kolkata, West Bengal, 700009, India

    Pulak Mondal

  2. Department of Electronics and Electrical Engineering, Indian Institute of Technology Kharagpur, Kharagpur, 721302, India

    Swapna Banerjee

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  1. Pulak Mondal
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  2. Swapna Banerjee
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Correspondence to Pulak Mondal.

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Mondal, P., Banerjee, S. FPGA-accelerated adaptive projection-based image registration. J Real-Time Image Proc 18, 113–125 (2021). https://doi.org/10.1007/s11554-020-00952-5

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