MCML (MOS Current Mode Logic) based implementation producing fast response and compliment output at the same time gives an impetus to the researcher to replace Bulk CMOS. Moreover, tremendous challenges faced by bulk CMOS at channel lengths below 45 nm induces a need to strive for a technological replacement of silicon in years to come. This introduces a zest in designer's mind to look for competent and novel substances to overcome the shortcoming of existing silicon. The future technology should be capable to deliver fast response, low power operation, scalable to reduced dimensions, and strong towards process variations. Carbon nanotube based technology (CNFET) is one of the reliable and competent alternative because it has most of these desired features and similar operating principle as that of CMOS. And hence, this research article focuses on a relative evaluation of CMOS and CNFET version of 3 bit parity checker at 16-nm technology nodes. The CNFET based 3 bit parity checker is faster (9.75×), it offers improvement in power dissipation (11.93×), improvement in PDP (116.39×), improvement in EDP (1135.76×) compared to CMOS counterpart. Scaling down the device emerges with a challenge of variability, just as power, delay and area, variability also has an impact on performance of the circuit. Technology scaling has significant consequences such as wider variation. This research article also presents variability analysis, in terms of delay (t_p) and power-delay product (PDP) for the proposed CNFET based MCML 3 bit Parity checker circuit. Extensive simulation using 16-nm technology node are carried out by loading two nominal copies of 'CNFET based MCML 3 bit Parity checker' (Circuit under Test) at either ends—input and output. This simulation framework supports the high level integration where stand alone operation has no application in the industry. The intent of this research is to investigate the circuit with minimal variability to propagation delay and PDP. The proposed ‘CNFET based MCML 3 bit parity checker’ exhibits improvement in delay (14.01×) and improvement in PDP (242.1×) variability as compared to CMOS counterpart. Thus, the CNFET based implementation emerges out as a robust circuit showing narrower spread in variability analysis against applied V_DD.

基于MCML（MOS电流模式逻辑）的实现方式可同时产生快速响应和补偿输出，这为研究人员取代Bulk CMOS提供了动力。此外，在小于45 nm的沟道长度下，体CMOS面临的巨大挑战引发了在未来几年内努力寻求硅技术替代的需求。这在设计人员的脑海中引起了人们的兴趣，他们正在寻找能胜任和新颖的物质来克服现有硅的缺点。未来的技术应该能够提供快速响应，低功耗运行，可扩展至缩小尺寸以及强大的工艺变化能力。基于碳纳米管的技术（CNFET）是可靠而有效的替代方法之一，因为它具有上述大多数所需功能，并且具有与CMOS相似的工作原理。因此，本文主要研究16纳米技术节点上CMOS和CNFET版本的3位奇偶校验器的相对评估。与CMOS同类产品相比，基于CNFET的3位奇偶校验器速度更快（9.75倍），在功耗（11.93倍），PDP（116.39倍）和EDP（1135.76倍）方面得到了改善。缩小器件尺寸面临着可变性的挑战，就像功率，延迟和面积一样，可变性也会影响电路的性能。技术扩展具有重大后果，例如变化范围更大。这篇研究文章还提供了关于延迟（t 与CMOS相比，PDP的改善（116.39倍），EDP的改善（1135.76倍）。缩小器件规模面临着可变性的挑战，就像功率，延迟和面积一样，可变性也会影响电路的性能。技术扩展具有重大后果，例如变化范围更大。这篇研究文章还提供了关于延迟（t 与CMOS相比，PDP的改善（116.39倍），EDP的改善（1135.76倍）。缩小器件规模面临着可变性的挑战，就像功率，延迟和面积一样，可变性也会影响电路的性能。技术扩展具有重大后果，例如变化范围更大。这篇研究文章还提供了关于延迟（t_（p）和功率延迟乘积（PDP），用于基于CNFET的MCML 3位奇偶校验器电路。通过在两端输入“基于CNFET的MCML 3位奇偶校验器”（被测电路）的两个标称副本来进行使用16-nm技术节点的广泛仿真。该仿真框架支持高级集成，在这种情况下，独立运行在行业中没有应用。本研究的目的是研究对传播延迟和PDP具有最小变化的电路。提出的基于CNFET的MCML 3位奇偶校验器与CMOS同类产品相比，的延迟时间提高了（14.01x），PDP可变性提高了（242.1x）。因此，基于CNFET的实施方案表现为一种鲁棒性电路，在针对所施加的V _DD的变异性分析中显示出较窄的展宽。