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Ultra high speed and novel design of power-aware CNFET based MCML 3-bit parity checker

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Abstract

MCML (MOS Current Mode Logic) based implementation producing fast response and compliment output at the same time gives an impetus to the researcher to replace Bulk CMOS. Moreover, tremendous challenges faced by bulk CMOS at channel lengths below 45 nm induces a need to strive for a technological replacement of silicon in years to come. This introduces a zest in designer's mind to look for competent and novel substances to overcome the shortcoming of existing silicon. The future technology should be capable to deliver fast response, low power operation, scalable to reduced dimensions, and strong towards process variations. Carbon nanotube based technology (CNFET) is one of the reliable and competent alternative because it has most of these desired features and similar operating principle as that of CMOS. And hence, this research article focuses on a relative evaluation of CMOS and CNFET version of 3 bit parity checker at 16-nm technology nodes. The CNFET based 3 bit parity checker is faster (9.75×), it offers improvement in power dissipation (11.93×), improvement in PDP (116.39×), improvement in EDP (1135.76×) compared to CMOS counterpart. Scaling down the device emerges with a challenge of variability, just as power, delay and area, variability also has an impact on performance of the circuit. Technology scaling has significant consequences such as wider variation. This research article also presents variability analysis, in terms of delay (tp) and power-delay product (PDP) for the proposed CNFET based MCML 3 bit Parity checker circuit. Extensive simulation using 16-nm technology node are carried out by loading two nominal copies of 'CNFET based MCML 3 bit Parity checker' (Circuit under Test) at either ends—input and output. This simulation framework supports the high level integration where stand alone operation has no application in the industry. The intent of this research is to investigate the circuit with minimal variability to propagation delay and PDP. The proposed ‘CNFET based MCML 3 bit parity checker’ exhibits improvement in delay (14.01×) and improvement in PDP (242.1×) variability as compared to CMOS counterpart. Thus, the CNFET based implementation emerges out as a robust circuit showing narrower spread in variability analysis against applied VDD.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Indira Gandhi Delhi Technical University for Women, New Delhi, India

    Pragya Srivastava & Richa Yadav

  2. Department of Electronics and Communication Engineering, KIET group of Institutions, Ghaziabad, India

    Richa Srivastava

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  1. Pragya Srivastava
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Correspondence to Richa Yadav.

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Srivastava, P., Yadav, R. & Srivastava, R. Ultra high speed and novel design of power-aware CNFET based MCML 3-bit parity checker. Analog Integr Circ Sig Process 104, 321–329 (2020). https://doi.org/10.1007/s10470-020-01609-w

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