Abstract

An energy-efficient capacitor switching scheme is proposed for successive approximation register analog-to-digital converter. During the design process, the semi-resting DAC structure and charge characteristic of floating capacitor ensure significant energy saving. There is no switching power consumption in the first two comparison process. Compared with the conventional switching scheme, the proposed method decreases 99.79% switching energy and 73.8% capacitor area. Benefit from merge-and-split method, only two reference levels are utilized in this novel scheme, where the power and accuracy of generating the third reference voltage are not necessary to consider. Besides, the reset energy of the proposed scheme is verified to be 0. Furthermore, the common mode voltage at comparator inputs is kept at 0.5V_ref except merely a 0.5LSB reduction due to LSB-down technique.

中文翻译：

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SAR ADC无需第三参考电平和复位能量的99.79％节能切换方案

摘要

提出了一种用于逐次逼近寄存器模数转换器的节能电容器切换方案。在设计过程中，半静态DAC结构和浮动电容器的充电特性可确保大量节能。在前两个比较过程中没有开关功耗。与传统的开关方案相比，该方法减少了99.79％的开关能量和73.8％的电容器面积。受益于合并和分割方法，在该新颖方案中仅使用两个参考电平，而无需考虑产生第三参考电压的功率和精度。此外，该方案的复位能量被验证为0。此外，比较器输入端的共模电压保持在0.5V _ref 除了由于LSB下降技术而仅减少0.5LSB之外。