The choice of multiplier and accumulation unit determines the performance of digital signal processors, particularly in Big-Data correlators employed in radio interferometers. This work is targeted towards reducing the multiplier-size and delay in order to achieve low-power and compact-area for interferometer correlators such as in SKA and VLBI. For this purpose different fast and hardware efficient algorithms are compared and combined to achieve a new optimized ASIC multiplier design for performing correlation in radio interferometry. Further, the optimized new multiplier design is incorporated into our previous correlation processing cell designs of CMAC, CoSMAC and PE in Balu and Hasan: IEEE. Access. 5 25353–25364, 2017. The improvement in performance is verified using the GlobalFoundries 28 nm HPP standard cell library.

中文翻译：

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28 nm CMOS 中全新优化的 ASIC 乘法器，用于处理无线电干涉测量中 FX 相关器的 X 部分

乘法器和累加器的选择决定了数字信号处理器的性能，特别是在无线电干涉仪中使用的大数据相关器中。这项工作的目标是减少乘法器的大小和延迟，以实现 SKA 和 VLBI 等干涉仪相关器的低功耗和紧凑区域。为此，将不同的快速和硬件高效算法进行比较和组合，以实现新的优化 ASIC 乘法器设计，用于在无线电干涉测量中执行​​相关。此外，优化的新乘法器设计被纳入我们之前在 Balu 和 Hasan：IEEE 的 CMAC、CoSMAC 和 PE 相关处理单元设计。使用权。5 25353–25364, 2017。使用 GlobalFoundries 28 nm HPP 标准单元库验证了性能的改进。