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New optimized ASIC multiplier in 28 nm CMOS for processing the X-part of FX correlator in radio interferometry

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Abstract

The choice of multiplier and accumulation unit determines the performance of digital signal processors, particularly in Big-Data correlators employed in radio interferometers. This work is targeted towards reducing the multiplier-size and delay in order to achieve low-power and compact-area for interferometer correlators such as in SKA and VLBI. For this purpose different fast and hardware efficient algorithms are compared and combined to achieve a new optimized ASIC multiplier design for performing correlation in radio interferometry. Further, the optimized new multiplier design is incorporated into our previous correlation processing cell designs of CMAC, CoSMAC and PE in Balu and Hasan: IEEE. Access. 5 25353–25364, 2017. The improvement in performance is verified using the GlobalFoundries 28 nm HPP standard cell library.

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  1. Center for Research in Analog and VLSI microsystem dEsign (CRAVE), School of Advanced Technology, Massey University, ROOM: AV 2.3, Albany Village Level-2, Albany, Auckland, 0632, New Zealand

    Vignesh Raja Balu & S. M. Rezaul Hasan

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  1. Vignesh Raja Balu
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  2. S. M. Rezaul Hasan
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Correspondence to S. M. Rezaul Hasan.

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Balu, V.R., Hasan, S.M.R. New optimized ASIC multiplier in 28 nm CMOS for processing the X-part of FX correlator in radio interferometry. Exp Astron 47, 325–343 (2019). https://doi.org/10.1007/s10686-019-09630-2

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