Look-up tables (LUT) form the basic logic elements in a large class of modern day field programmable gate arrays (FPGA). With FPGAs increasingly being used in low and medium volume productions, many vendors have improved the capacity and versatility of these devices. The enormous logic capacity inherent in state-of-art FPGAs has made it essential to develop automated computer aided design (CAD) support for logic synthesis using these platforms. Since design entry is the only manual phase in the FPGA CAD-flow, it essentially rules out any scope for technology-dependent optimization, which focusses on achieving optimal mapping of logical functionalities onto the target platforms. Evidently, majority of the work related to the implementation of different arithmetic circuits on FPGAs focuses only on the technology-independent optimizations, where the design process consists of modifying the architecture at the top level without giving any consideration to the mapping of the architecture onto the FPGA device. In this paper, we consider the technology-dependent optimization of the fixed-point bit-parallel multipliers on LUT based FPGAs. Our approach re-structures the initial Boolean network and transforms it into an optimized LUT netlist prior to the design entry phase. The design entry of the optimized netlist is then carried out using instantiation based coding styles. This ensures that the optimizations done prior to the design entry phase remain preserved throughout the synthesis process. We particularly focus on 6-input LUTs that are inherent basic logic elements in state-of-art FPGAs. Theoretical analysis and detailed experimentation using state-of-art Xilinx 7th generation FPGAs reveal a substantial speed-up in performance.

中文翻译：

---

针对最新FPGA的基于LUT的定点乘法器实现

查找表（LUT）构成了一大类现代现场可编程门阵列（FPGA）中的基本逻辑元素。随着FPGA在中小批量生产中的使用越来越多，许多供应商已经提高了这些设备的容量和多功能性。先进的FPGA固有的巨大逻辑容量使使用这些平台开发用于逻辑综合的自动化计算机辅助设计（CAD）支持变得至关重要。由于设计输入是FPGA CAD流程中唯一的手动阶段，因此它实质上排除了与技术相关的优化的任何范围，该范围专注于实现逻辑功能到目标平台的最佳映射。显然，与在FPGA上实现不同算术电路有关的大部分工作仅集中在与技术无关的优化上，设计过程包括在顶层修改架构，而不考虑架构到FPGA器件的映射。在本文中，我们考虑了基于LUT的FPGA上定点位并行乘法器的技术相关优化。在设计进入阶段之前，我们的方法将重新构造初始布尔网络，并将其转换为优化的LUT网表。然后，使用基于实例的编码样式来执行优化网表的设计条目。这样可以确保在设计进入阶段之前完成的优化在整个综合过程中都得以保留。我们特别关注于6输入LUT，它们是最新型FPGA中固有的基本逻辑元素。