Skip to main content
SpringerLink
Log in

LUT based realization of fixed-point multipliers targeting state-of-art FPGAs

  • Published:
Design Automation for Embedded Systems Aims and scope Submit manuscript

Abstract

Look-up tables (LUT) form the basic logic elements in a large class of modern day field programmable gate arrays (FPGA). With FPGAs increasingly being used in low and medium volume productions, many vendors have improved the capacity and versatility of these devices. The enormous logic capacity inherent in state-of-art FPGAs has made it essential to develop automated computer aided design (CAD) support for logic synthesis using these platforms. Since design entry is the only manual phase in the FPGA CAD-flow, it essentially rules out any scope for technology-dependent optimization, which focusses on achieving optimal mapping of logical functionalities onto the target platforms. Evidently, majority of the work related to the implementation of different arithmetic circuits on FPGAs focuses only on the technology-independent optimizations, where the design process consists of modifying the architecture at the top level without giving any consideration to the mapping of the architecture onto the FPGA device. In this paper, we consider the technology-dependent optimization of the fixed-point bit-parallel multipliers on LUT based FPGAs. Our approach re-structures the initial Boolean network and transforms it into an optimized LUT netlist prior to the design entry phase. The design entry of the optimized netlist is then carried out using instantiation based coding styles. This ensures that the optimizations done prior to the design entry phase remain preserved throughout the synthesis process. We particularly focus on 6-input LUTs that are inherent basic logic elements in state-of-art FPGAs. Theoretical analysis and detailed experimentation using state-of-art Xilinx 7th generation FPGAs reveal a substantial speed-up in performance.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17
Fig. 18
Fig. 19
Fig. 20
Fig. 21
Fig. 22
Fig. 23
Fig. 24
Fig. 25
Fig. 26
Fig. 27

Similar content being viewed by others

References

  1. Narayan GL, Venkataramani B (2005) Optimization techniques for FPGA based wave pipelined DSP blocks. IEEE Trans Very Large Scale Integr (VLSI) Syst 13(7):783–792

    Article  Google Scholar 

  2. Ashour MA, Saleh HI (2000) An FPGA implementation guide for some different types of serial-parallel multiplier structures. Microelectron J 31:161–168

    Article  Google Scholar 

  3. Compton K, Hauck S (2002) Reconfigurable computing: a survey of systems and software. ACM Comput Surv 34(2):171–210

    Article  Google Scholar 

  4. Tessier R, Burleson W (2002) Reconfigurable computing and digital signal processing: past, present and future. In: Programmable digital signal processors, pp 147–186

  5. Woods R, McAllister J, Lightbody G, Yi Y (2008) FPGA-based implementation of signal processing systems. Wiley, Hoboken

    Book  Google Scholar 

  6. Tessier R, Burleson W (2001) Reconfigurable computing for DSP: a survey. J VLSI Signal Process 28:7–27

    Article  MATH  Google Scholar 

  7. Todman TJ, Constantinides GA, Wilton SJE, Mencer O, Luk W, Cheung PYK (2005) Reconfigurable computing: architecture and design methods. IEE Proc Comput Digit Tech 152(2):193–207

    Article  Google Scholar 

  8. Naseer R, Balakrishnan M, Kumar A (1998) Direct mapping of RTL structures onto LUT-based FPGAs. IEEE Trans Comput Aided Des Integr Circuits Syst 17(7):624–631

    Article  Google Scholar 

  9. Stitt G, Vahid F, Nematbakhsh S (2004) Energy savings and speed-ups from partitioning critical software loops to hardware in embedded systems. ACM Trans Embed Comput Syst 3(1):218–232

    Article  Google Scholar 

  10. Tse AHT, Thomas DB, Luk W (2011) Design exploration of quadrature methods in option pricing. IEEE Trans VLSI Syst 99:1–9

    Google Scholar 

  11. Kestur S, Davis JD, Williams O (2010) BLAS Comparison on FPGA, CPU and GPU. In: IEEE annual symposium on VLSI, pp 288–293

  12. Jaiswal MK, Cheung RCC (2013) Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support. Microelectron J 44:421–430

    Article  Google Scholar 

  13. Hauck S, Dehon A (2008) Reconfigurable computing: the theory and practice of FPGA-based computing. Morgan Kaufmann Series, Burlington

    MATH  Google Scholar 

  14. Brown SD, Rose J, Francis RJ, Vranesic ZG (1992) Field programmable gate arrays. Kluwer Academic Publisher, Dordrecht

    Book  MATH  Google Scholar 

  15. Ling A, Singh DP, Brown SD (2005) FPGA technology mapping: a study of optimality. In: IEEE proceedings design automation conference, pp 427–432

  16. Chen D, Cong, J (2004) DAO map: a depth-optimal area optimization mapping algorithm for FPGA designs. In: IEEE/ACM international conference on_computer aided design

  17. Rohleder R (1991) Marker overview: user programmable logic. In: In-Stat Services research report

  18. Anderson JH, Wang Q (2011) Area-efficient FPGA logic elements: architecture and synthesis. In: 16th Asia and South Pacific design automation conference (ASP-DAC)

  19. Francis R, Rose J, Vranesic Z (1991) Chortle-crf: fast technology mapping for lookup table-based FPGAs. In: Proceedings of the 28th ACM/IEEE design automation conference

  20. Murgai R, Shenoy N, Brayton RK, Vinccentelli AS (1991) Improved logic synthesis algorithms for table look up architectures. In: IEEE international conference on computer-aided design, ICCAD-91

  21. Karplus K (1991) Xmap: a technology mapper for table-lookup field-programmable gate arrays. In: 28th ACM/IEEE design automation conference, DAC, pp 240–243

  22. Woo NS (1991) A heuristic method for FPGA technology mapping based on the edge visibility. In: 28th ACM/IEEE design automation conference, DAC, pp 248–251

  23. Sawkar P, Thomas D (1992) Area and delay mapping for table-look-up based field programmable gate arrays. In: 29th ACM/IEEE design automation conference, DAC, pp 368–373

  24. Cong J, Wu C, Ding Y (1999) Cut ranking and pruning: enabling a general and efficient FPGA mapping solution. In: Proceedings of the 1999 ACM/SIGDA seventh international symposium on field programmable gate arrays, pp 29–35

  25. Francis R, Rose J, Vranesic Z (1991) Technology mapping for lookup table-based FPGA’s for performance. In: IEEE international conference on computer-aided design, ICCAD-91

  26. Murgai R, Shenoy N, Brayton RK, Vinccentelli AS (1991) Performance directed synthesis for table look up programmable gate arrays. In: IEEE international conference on computer-aided design, ICCAD-91, pp 11–14

  27. Chen KC, Cong J, Ding Y, Kahng AB (1992) DAG-map: graph-based FPGA technology mapping for delay optimization. IEEE Des Test Comput 9(3):7–20

    Article  Google Scholar 

  28. Cong J, Ding Y (1992) An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. In: IEEE international conference on computer-aided design, ICCAD

  29. Yang H, Wong DF (1994) Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs. In: IEEE international conference on computer-aided design ICCAD

  30. Pan P, Liu CL (1996) Optimal clock period FPGA technology mapping for sequential circuits. In: 33rd ACM/IEEE design automation conference, DAC

  31. Farrahi AH, Sarrafzadeh M (1994) FPGA technology mapping for power minimization. Field Program Logic Archit Synth Appl 849:66–77

    Google Scholar 

  32. Anderson JH, Najm FN (2002) Power-aware technology mapping for LUT-based FPGAs. In: Proceedings of IEEE international conference on field-programmable technology (FPT)

  33. Wang ZH, Liu EC, Lai J, Wang TC (2001) Power minimization in LUT-based FPGA technology mapping. In: Proceedings of Asia and South Pacific design automation conference ASP-DAC, pp 635–640

  34. Li H, Mak W, Katkoori S (2003) Efficient LUT-based FPGA technology mapping for power minimization. In: Proceedings of Asia and South Pacific design automation conference ASP-DAC, pp 353–358

  35. Lamoureux J, Wilton SJE (2003) On the interaction between power-aware CAD algorithms for FPGAs. In: International conference on computer aided design, ICCAD-2003, pp 701–708, 9–13

  36. Chen D, Cong J, Dong C, He L, Li F, Peng CC (2010) Technology mapping and clustering for FPGA architectures with dual supply voltages. IEEE Trans Comput Aided Des Integr Circuits Syst 29(11):1709–1722

    Article  Google Scholar 

  37. Cong J, Ding Y (1994) On area/depth trade-off in LUT-based FPGA technology mapping. IEEE Trans Very Large Scale Integr (VLSI) Syst 2(2):137–148

    Article  Google Scholar 

  38. Cong J, Hwang Y (1995) Simultaneous depth and area minimization in LUT-based FPGA mapping. In: Proceedings of the third international ACM symposium on field-programmable gate arrays, FPGA, p 95

  39. Legl C, Wurth B, Eckl K (1996) A Boolean approach to performance-directed technology mapping for LUT-based FPGA designs. IN: Proceedings of the design automation conference, DAC, pp 730–733

  40. Cong J, Ding Y (1993) Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs. In: IEEE international conference on computer-aided design, ICCAD

  41. Chang SC, Marek-Sodowska M, Hwang T (1996) Technology mapping for TLU FPGA based on decomposition of binary decision diagrams. IEEE Trans Comput Aided Des Integr Circuits Syst 15(10):1226–1236

    Article  Google Scholar 

  42. Deng L, Sobti K, Zhang Y, Chakarbarti C (2011) Accurate area, time and power models for FPGA based implementations. J Signal Process Syst 63(1):39–50

    Article  Google Scholar 

  43. Kamboh HM, Khan SA (2012) FPGA implementation of fast adder. In: Proceeding of the 7th international conference on computing and convergence technology, pp 1324–1327

  44. Parhi KK (1999) VLSI digital signal processing systems design and implementation. Wiley, Hoboken

    Google Scholar 

  45. Chang CH, Satzoda RK (2010) A low error and high performance multiplexer based truncated multiplier. IEEE Trans Very Large Scale Integr (VLSI) Syst 18(12):1767–1771

    Article  Google Scholar 

  46. Kidambi SS, Guibaly FE, Antoniou A (1996) Area-efficient multipliers for digital signal processing applications. IEEE Trans Circuits Syst II Analog Digit Signal Process 43(2):90–95

    Article  Google Scholar 

  47. Stine JE, Duverne OM (2003) Variations on truncated multiplication. In: Proceedings of the euromicro symposium on digital system design

  48. Baugh CR, Wooley B (1973) A two’s complement parallel array multiplication algorithm. IEEE Trans Comput C–22(12):1045–1047

    Article  MATH  Google Scholar 

  49. Keutzer K (1987) DAGON: technology binding and local optimization by DAG matching. In: Proceedings 24th DAC, pp 341–347

  50. Detjens E, Gannot G, Rudell R, Vincentelli AS, Wang A (1987) Technology mapping in MIS. In: Proceedings ICCAD-87, pp 116–119

  51. http://www.xilinx.com/product/design-tools/vivado.html

  52. http://www.xilinx.com/support/download.html

  53. Bhattacharjee S, Sil S, Basak B, Chakarbarti A (2011) Evaluation of power efficient adder and multiplier circuits for FPGA based DSP applications. In: International conference on communication and industrial application (ICCIA)

  54. Pradhan M, Panda R (2014) High speed multiplier using Nikhilam Sutra algorithm of Vedic mathematics. Int J Electron 101(13):300–307

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Computer Science and Engineering, NIT, Srinagar, India

    Burhan Khurshid

Authors
  1. Burhan Khurshid
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Burhan Khurshid.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Khurshid, B. LUT based realization of fixed-point multipliers targeting state-of-art FPGAs. Des Autom Embed Syst 21, 89–115 (2017). https://doi.org/10.1007/s10617-017-9184-x

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10617-017-9184-x

Keywords

Search

Navigation