This paper presents a 12-bit 120-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with improved split capacitive DAC and low-noise dynamic comparator. A split DAC structure with parasitic capacitance depressed technique is introduced, the top-plate parasitic capacitances of MSB and LSB DAC arrays are both reduced, and the accuracy of split DAC is increased without calibration. Further, an optimized sampling method is used to provide a unit capacitance between the MSB and LSB DAC arrays, the match of DAC is improved. In addition, a high-speed dynamic comparator with input-referred noise reduction technique is proposed, an extra positive feedback loop is provided to reduce the comparison delay and the gain of the comparator is also increased to depress noise. To demonstrate the proposed techniques, a design of SAR ADC is fabricated in 65-nm CMOS technology, consuming 6 mW from 1.2 V power supply with a SNDR > 66.1 dB and SFDR > 81.5 dB. The proposed ADC core occupies an active area of 0.05 mm², and the corresponding FoM is 30 fJ/conversion-step with Nyquist frequency.

中文翻译：

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具有改进的分离电容式DAC和低噪声动态比较器的12位120-MS / s SAR ADC

本文提出了一种12位120-MS / s逐次逼近寄存器（SAR）模数转换器（ADC），具有改进的分离电容DAC和低噪声动态比较器。介绍了采用寄生电容抑制技术的分离式DAC结构，降低了MSB和LSB DAC阵列的顶板寄生电容，并且无需校准即可提高分离式DAC的精度。此外，使用优化的采样方法在MSB和LSB DAC阵列之间提供单位电容，从而改善了DAC的匹配度。另外，提出了一种具有输入参考噪声降低技术的高速动态比较器，提供了一个额外的正反馈环路来减少比较延迟，并且还增加了比较器的增益以抑制噪声。为了演示建议的技术，SAR ADC的设计采用65 nm CMOS技术制造，从1.2 V电源消耗6 mW的功率，SNDR> 66.1 dB，SFDR> 81.5 dB。拟议的ADC核心占据0.05毫米的有效面积²，对应的FoM为30 fJ /转换步长（奈奎斯特频率）。