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A 12-bit 120-MS/s SAR ADC with improved split capacitive DAC and low-noise dynamic comparator

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Abstract

This paper presents a 12-bit 120-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with improved split capacitive DAC and low-noise dynamic comparator. A split DAC structure with parasitic capacitance depressed technique is introduced, the top-plate parasitic capacitances of MSB and LSB DAC arrays are both reduced, and the accuracy of split DAC is increased without calibration. Further, an optimized sampling method is used to provide a unit capacitance between the MSB and LSB DAC arrays, the match of DAC is improved. In addition, a high-speed dynamic comparator with input-referred noise reduction technique is proposed, an extra positive feedback loop is provided to reduce the comparison delay and the gain of the comparator is also increased to depress noise. To demonstrate the proposed techniques, a design of SAR ADC is fabricated in 65-nm CMOS technology, consuming 6 mW from 1.2 V power supply with a SNDR > 66.1 dB and SFDR > 81.5 dB. The proposed ADC core occupies an active area of 0.05 mm2, and the corresponding FoM is 30 fJ/conversion-step with Nyquist frequency.

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Authors and Affiliations

  1. School of Shuozhou, North University of China, Taiyuan, 030051, People’s Republic of China

    Tian-ye Liu, Huifang Niu & Qing Meng

  2. School of Microelectronics and Solid-State Electronics, University of Electronic Science and Technology of China, Chengdu, 611731, People’s Republic of China

    Daiguo Xu

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  1. Tian-ye Liu
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  2. Daiguo Xu
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  4. Qing Meng
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Correspondence to Daiguo Xu.

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Liu, Ty., Xu, D., Niu, H. et al. A 12-bit 120-MS/s SAR ADC with improved split capacitive DAC and low-noise dynamic comparator. Analog Integr Circ Sig Process 102, 403–413 (2020). https://doi.org/10.1007/s10470-019-01581-0

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  • DOI: https://doi.org/10.1007/s10470-019-01581-0

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