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Enhanced test algorithm for nanoelectronic Resistive Random Access Memory testing using self check write scheme
Analog Integrated Circuits and Signal Processing ( IF 1.2 ) Pub Date : 2020-01-01 , DOI: 10.1007/s10470-019-01576-x
H. Sribhuvaneshwari , Suthendran Kannan

Emerging nanoelectronic memories such as PCRAM, STT-RAM, Ferroelectric FET Memory and Resistive Random Access Memory (RRAM) are proficient to substitute the traditional memory technologies such as SRAMs, DRAMs and flash memory in future computers. Among all these nanoelectronic memories RRAM (combines the merits of both RAM and Flash memories) is exceptionally fast, cost-effective which is capable of accomplishing the requirements of immense growth in data and storage. Despite the fact that it suffers by various faults, more specifically Write Disturbance Fault (WDF) and Read Disturbance Fault (RDF) has huge effect on system performance and reliability. Different algorithms are designed to identify specific kind of faults and the main drawback of all existing algorithm is redundancy (repeated March elements with write and read operations) it will increase the test complexity and time. Moreover, this repeated write and read operation will leads to endurance degradation. To circumvent this pitfall, a self-checking write circuit is adapted where the accuracy of every write operation is verified at the end of write cycle by means of a write verification signal in the write circuit (acts as in built read circuit). Hence, this self checking write method offers a combined “write and read” operation (wr) that detects the faulty write operation (main reason for read fault) and avoids the data corruption in memory system. To the best of our knowledge, we are the first one to propose March algorithm with “wr” element hence it is named as novel ‘March WR’ testing algorithm which detects WDF and RDF effectively with 4n test complexity which is very less than all other existing test algorithms. Thus it reduces 63.63% of the test time. Due to keen monitoring of each operation 100% fault coverage is achieved that results in enhanced performance and reliability.



中文翻译:

使用自检写方案的纳米电子电阻式随机存取存储器测试的增强测试算法

新兴的纳米电子存储器,例如PCRAM,STT-RAM,铁电FET存储器和电阻性随机存取存储器(RRAM)能够熟练替代未来计算机中的SRAM,DRAM和闪存等传统存储技术。在所有这些纳米电子存储器中,RRAM(结合了RAM和闪存的优点)非常快速,具有成本效益,能够满足数据和存储巨大增长的需求。尽管存在各种故障,但特别是写干扰故障(WDF)和读干扰故障(RDF)对系统性能和可靠性有巨大影响。设计了不同的算法来识别特定类型的故障,所有现有算法的主要缺点是冗余(重复的March元素具有读写操作),这会增加测试的复杂性和时间。而且,这种重复的写和读操作将导致耐久性下降。为了避免这种缺陷,采用了一种自检查式写电路,其中在写周期结束时,通过写电路中的写验证信号来验证每个写操作的准确性(作用与内置的读电路相同)。因此,这种自检查式写方法提供了组合的“写和读”操作(wr),该操作可检测错误的写操作(导致读错误的主要原因)并避免内存系统中的数据损坏。据我们所知,我们是第一个提出带有“ wr”元素的March算法的人,因此被称为新颖的“ March WR”测试算法,该算法以4n的测试复杂度有效检测WDF和RDF,这比其他所有现有测试算法都要少。因此,它减少了63.63%的测试时间。通过对每个操作的敏锐监控,可以实现100%的故障覆盖率,从而提高性能和可靠性。

更新日期:2020-01-01
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