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Enhanced test algorithm for nanoelectronic Resistive Random Access Memory testing using self check write scheme

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Abstract

Emerging nanoelectronic memories such as PCRAM, STT-RAM, Ferroelectric FET Memory and Resistive Random Access Memory (RRAM) are proficient to substitute the traditional memory technologies such as SRAMs, DRAMs and flash memory in future computers. Among all these nanoelectronic memories RRAM (combines the merits of both RAM and Flash memories) is exceptionally fast, cost-effective which is capable of accomplishing the requirements of immense growth in data and storage. Despite the fact that it suffers by various faults, more specifically Write Disturbance Fault (WDF) and Read Disturbance Fault (RDF) has huge effect on system performance and reliability. Different algorithms are designed to identify specific kind of faults and the main drawback of all existing algorithm is redundancy (repeated March elements with write and read operations) it will increase the test complexity and time. Moreover, this repeated write and read operation will leads to endurance degradation. To circumvent this pitfall, a self-checking write circuit is adapted where the accuracy of every write operation is verified at the end of write cycle by means of a write verification signal in the write circuit (acts as in built read circuit). Hence, this self checking write method offers a combined “write and read” operation (wr) that detects the faulty write operation (main reason for read fault) and avoids the data corruption in memory system. To the best of our knowledge, we are the first one to propose March algorithm with “wr” element hence it is named as novel ‘March WR’ testing algorithm which detects WDF and RDF effectively with 4n test complexity which is very less than all other existing test algorithms. Thus it reduces 63.63% of the test time. Due to keen monitoring of each operation 100% fault coverage is achieved that results in enhanced performance and reliability.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Kalasalingam Academy of Research and Education, Krishnankoil, Tamil Nadu, India

    H. Sribhuvaneshwari

  2. Department of Information Technology, Kalasalingam Academy of Research and Education, Krishnankoil, Tamil Nadu, India

    Suthendran Kannan

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Sribhuvaneshwari, H., Kannan, S. Enhanced test algorithm for nanoelectronic Resistive Random Access Memory testing using self check write scheme. Analog Integr Circ Sig Process 104, 145–155 (2020). https://doi.org/10.1007/s10470-019-01576-x

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