Two-dimensional semiconductors could be used as a channel material in low-power transistors, but the deposition of high-quality, ultrathin high-κ dielectrics on such materials has proved challenging. In particular, atomic layer deposition typically leads to non-uniform nucleation and island formation, creating a porous dielectric layer that suffers from current leakage, particularly when the equivalent oxide thickness is small. Here, we report the atomic layer deposition of high-κ gate dielectrics on two-dimensional semiconductors using a monolayer molecular crystal as a seeding layer. The approach can be used to grow dielectrics with an equivalent oxide thickness of 1 nm on graphene, molybdenum disulfide (MoS₂) and tungsten diselenide (WSe₂). Compared with dielectrics created using established methods, our dielectrics exhibit a reduced roughness, density of interface states and leakage current, as well as an improved breakdown field. With the technique, we fabricate graphene radio-frequency transistors that operate at 60 GHz, and MoS₂ and WSe₂ complementary metal–oxide–semiconductor transistors with a supply voltage of 0.8 V and subthreshold swing down to 60 mV dec⁻¹. We also create MoS₂ transistors with a channel length of 20 nm, which exhibit an on/off ratio of over 10⁷.

二维半导体可以用作低功率晶体管的沟道材料，但是在这种材料上沉积高质量，超薄高κ电介质已证明是一项挑战。特别地，原子层沉积通常导致不均匀的成核和岛的形成，从而形成遭受电流泄漏的多孔介电层，特别是当等效氧化物厚度小时。在这里，我们报告了使用单层分子晶体作为籽晶层的二维半导体上高κ栅极电介质的原子层沉积。该方法可用于在石墨烯，二硫化钼（MoS ₂）和二硒化钨（WSe ₂）上生长等效氧化物厚度为1 nm的电介质）。与使用既定方法创建的电介质相比，我们的电介质显示出降低的粗糙度，界面态密度和泄漏电流，以及改善的击穿场。利用该技术，我们可以制造工作在60 GHz的石墨烯射频晶体管，以及MoS ₂和WSe ₂互补金属氧化物半导体晶体管，这些晶体管的电源电压为0.8 V，亚阈值的摆幅下降至60 mV dec ^-1。我们还创建了沟道长度为20 nm的MoS ₂晶体管，其开/关比超过10 ⁷。