当前位置: X-MOL 学术IEEE Electron Device Lett. › 论文详情
Our official English website, www.x-mol.net, welcomes your feedback! (Note: you will need to create a separate account there.)
Simulation of Transport Moiré Pattern in Van Der Waals Heterostructures
IEEE Electron Device Letters ( IF 4.1 ) Pub Date : 2023-01-30 , DOI: 10.1109/led.2023.3240471
Xiangnan Li 1 , Yawei Lv 1 , Qingjun Tong 1 , Lei Liao 2 , Kenli Li 3 , Changzhong Jiang 4
Affiliation  

Vertically stacking two-dimensional (2D) materials with different lattice constants will generate a Moiré pattern with a nanometer-scale periodicity. Here, we theoretically demonstrate the transport Moiré patterns on the surfaces of stacked 2D materials. In the MOSFET model, the electrons accumulate at high Moiré potential regions, while they dissipate at the others, along the gate voltage ( ${V}_{g}{)}$ until high current levels. As an application of the inhomogeneous transport, we show that the Moiré pattern can be used to restrain the effect of edge defects in one-dimensional ribbons by modulating the potentials of the edge and middle regions. Simulation results show that the ${V}_{g}$ deviations can be substantially reduced when different kinds of edge defects are randomly added, such as vacancies and foreign dopants, suggesting the suitability of Moiré pattern in defect engineering.

中文翻译:

范德瓦尔斯异质结构中传输莫尔图案的模拟

垂直堆叠具有不同晶格常数的二维 (2D) 材料将生成具有纳米级周期性的莫尔图案。在这里,我们从理论上展示了堆叠二维材料表面上的传输莫尔图案。在 MOSFET 模型中,电子在高莫尔电位区域聚集,而在其他区域沿着栅极电压消散( ${V}_{g}{)}$直到高电流水平。作为非均匀传输的应用,我们表明莫尔图案可用于通过调制边缘和中间区域的电位来抑制一维带中边缘缺陷的影响。仿真结果表明 ${V}_{g}$当随机添加不同类型的边缘缺陷(例如空位和外来掺杂剂)时,偏差可以大大减少,这表明莫尔图案在缺陷工程中的适用性。
更新日期:2023-01-30
down
wechat
bug