Polar codes have received growing attention in the past decade and have been selected as the coding scheme for the control channel in the fifth generation (5G) wireless communication systems. However, the conventional polar codes have only been constructed by binary (2x2) kernel which poses block length limitation to powers of 2. To attain more flexible block lengths, multi-kernel polar codes are proposed. In this paper, a combinational architecture for multi-kernel polar codes with high throughput is proposed based on successive cancellation decoding algorithm. The proposed scheme can decode pure-binary, pure-ternary (3x3), and binary-ternary mixed polar codes. The decoder's architecture is rate-flexible meaning that a new code rate can be assigned to the decoder at every clock cycle. The proposed architecture is validated by FPGA implementation and the results reveal that a code of size N=81 gains the coded throughput of 1664.5 Mbps. A novel Python-based polar compiler is also proposed to automatically generate the HDL modules for target decoders. A designer can input the target block length and kernel ordering of a polar code, and get the required VHDL files automatically. Based on our simulations, the majority of the required HDL files can be generated in less than 0.4 seconds.

中文翻译：

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用于多内核 Polar 代码的高吞吐率灵活组合解码器

极化码在过去十年中受到越来越多的关注，并被选为第五代（5G）无线通信系统中控制信道的编码方案。然而，传统的 Polar 码仅由二进制 (2x2) 内核构造，这将块长度限制为 2 的幂。为了获得更灵活的块长度，提出了多内核 Polar 码。本文提出了一种基于逐次抵消译码算法的高吞吐量多核极化码组合架构。所提出的方案可以解码纯二进制、纯三进制 (3x3) 和二进制-三进制混合极化码。解码器的架构是速率灵活的，这意味着可以在每个时钟周期为解码器分配一个新的码率。所提出的体系结构通过 FPGA 实现进行了验证，结果表明大小为 N=81 的代码获得了 1664.5 Mbps 的编码吞吐量。还提出了一种新颖的基于 Python 的 polar 编译器来自动为目标解码器生成 HDL 模块。设计人员可以输入一个polar代码的目标块长度和内核顺序，并自动得到所需的VHDL文件。根据我们的模拟，可以在不到 0.4 秒的时间内生成大部分所需的 HDL 文件。