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A Flexible and High-Performance Lattice-Based Post-Quantum Crypto Secure Coprocessor
IEEE Transactions on Industrial Informatics ( IF 12.3 ) Pub Date : 2022-08-25 , DOI: 10.1109/tii.2022.3195743
Aobo Li 1 , Dongsheng Liu 1 , Cong Zhang 1 , Xiang Li 1 , Shuo Yang 1 , Xingjie Liu 1 , Jiahao Lu 1 , Xuecheng Zou 1 , Ang Hu 1 , Tianming Ni 2
Affiliation  

Progress of quantum computing technology seriously threaten the industrial information security based on traditional public-key cryptosystem. Thus, the cryptosystem with anti-quantum attack characteristics is gradually becoming a significant research in the security field. In this article, a flexible and high-performance secure coprocessor is designed for security in industrial processes, which can execute the post-quantum cryptographic algorithm Saber efficiently. Custom instruction set and arithmetic accelerators are proposed to effectively optimize the flexibility of system architecture, and improve the performance of calculation. The hardware implementation results show that the maximum operating frequency of the coprocessor can reach 345 MHz. Compared with related state-of-the-art works, it achieves the highest operating frequency on the same Xilinx UltraScale+ FPGA platform, performing the encryption and decryption operations within 13.5 and 15.4 μ s, respectively. Meanwhile, this article achieves 1.7/3.1/5.9× area-time product improvements in look-up table flip-flop block memory storage with good flexibility.

中文翻译:

一种灵活且高性能的基于格的后量子加密安全协处理器

量子计算技术的进步严重威胁着基于传统公钥密码体制的工业信息安全。因此,具有抗量子攻击特性的密码体制正逐渐成为安全领域的一项重要研究。在本文中,针对工业过程中的安全设计了一种灵活的高性能安全协处理器,可以高效地执行后量子密码算法 Saber。提出定制指令集和算术加速器,有效优化系统架构的灵活性,提高计算性能。硬件实现结果表明协处理器最高工作频率可达345 MHz。与相关的最先进的作品相比,分别为 μ s。同时,本文在查找表触发器块内存存储中实现了1.7/3.1/5.9×面积-时间乘积改进,具有良好的灵活性。
更新日期:2022-08-25
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