We review the problem of automating hardware-aware architectural design process of Deep Neural Networks (DNNs). The field of Convolutional Neural Network (CNN) algorithm design has led to advancements in many fields, such as computer vision, virtual reality, and autonomous driving. The end-to-end design process of a CNN is a challenging and time-consuming task, as it requires expertise in multiple areas such as signal and image processing, neural networks, and optimization. At the same time, several hardware platforms, general- and special-purpose, have equally contributed to the training and deployment of these complex networks in a different setting. Hardware-Aware Neural Architecture Search (HW-NAS) automates the architectural design process of DNNs to alleviate human effort and generate efficient models accomplishing acceptable accuracy-performance tradeoffs. The goal of this article is to provide insights and understanding of HW-NAS techniques for various hardware platforms (MCU, CPU, GPU, ASIC, FPGA, ReRAM, DSP, and VPU), followed by the co-search methodologies of neural algorithm and hardware accelerator specifications.

我们回顾了深度神经网络 (DNN) 的自动化硬件感知架构设计过程的问题。卷积神经网络 (CNN) 算法设计领域带动了计算机视觉、虚拟现实和自动驾驶等许多领域的进步。CNN 的端到端设计过程是一项具有挑战性且耗时的任务，因为它需要信号和图像处理、神经网络和优化等多个领域的专业知识。与此同时，一些通用和专用硬件平台同样有助于在不同环境中训练和部署这些复杂网络。硬件感知神经架构搜索(HW-NAS) 使 DNN 的架构设计过程自动化，以减轻人力并生成高效模型，实现可接受的准确性-性能权衡。本文的目的是提供对各种硬件平台（MCU、CPU、GPU、ASIC、FPGA、ReRAM、DSP 和 VPU）的 HW-NAS 技术的见解和理解，然后是神经算法和硬件加速器规格。