In order to reduce the specific ON resistance ( $\text{R}_{\mathbf {{ \mathrm{\scriptscriptstyle ON}},sp}}$ ) of power device in the drift region, the folded accumulation lateral double-diffused MOSFET (FALDMOS) is manufactured and analyzed in this article. The drift region of the FALDMOS is etched to form the folded surface, which is similar to the FinFET structure. The oxide inside the trench optimizes the electric field in the drift region, so the doping concentration can be increased while maintaining the breakdown voltage (BV). In addition, the trench increases the area of the drift region covered by the extended gate electrode, which can introduce more accumulated electrons when the device is turned on. The increased doping concentration and accumulated electrons work together to substantially increase the conductivity of the drift region, thereby obtaining ultralow $\text{R}_{ \mathrm{\scriptscriptstyle ON},sp}$ . Furthermore, the folded accumulation LDMOS with split gate (FSLDMOS) is proposed to solve the phenomenon that the BV of the FALDMOS cannot be improved by increasing the drift length with the fixed oxide thickness. The polysilicon above the drift region is etched apart to form an extended gate and a split electrode. The electric field concentration near the drain can be alleviated by adjusting the bias on the split electrode. The FALDMOS and FSLDMOS are manufactured by the 0.35- $\mu \text{m}$ BCD technology and the key processes, such as trench etching and polysilicon filling, are shown. The experimental results show that $\text{R}_{ \mathrm{\scriptscriptstyle ON},sp}$ of the FALDMOS is only 9.3 $\text{m}\Omega \cdot $ mm2, while that the conventional LDMOS is 36.2 $\text{m}\Omega \cdot $ mm2, which is reduced by 74.3% with the same BV of 36 V. Moreover, the current density of FALDMOS is five times higher than that of the conventional LDMOS in the same areas. The BV of the FSLDMOS is improved by 66% compared with FALDMOS.

中文翻译：

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累积模式器件：具有折叠漂移区的 LDMOS 实验可实现超低比导通电阻


为了降低漂移区功率器件的比导通电阻( $\text{R}_{\mathbf {{ \mathrm{\scriptscriptstyle ON}},sp}}$ )，折叠积累横向双扩散本文对 MOSFET (FALDMOS) 进行了制造和分析。 FALDMOS的漂移区被蚀刻形成折叠表面，这与FinFET结构类似。沟槽内的氧化物优化了漂移区的电场，因此可以在保持击穿电压（BV）的同时增加掺杂浓度。此外，沟槽增加了被延伸的栅电极覆盖的漂移区的面积，这可以在器件开启时引入更多积累的电子。增加的掺杂浓度和积累的电子共同作用，大大提高了漂移区的电导率，从而获得超低 $\text{R}_{ \mathrm{\scriptscriptstyle ON},sp}$ 。此外，为了解决FALDMOS在固定氧化层厚度的情况下无法通过增加漂移长度来提高BV的现象，提出了带有分裂栅的折叠累积LDMOS（FSLDMOS）。漂移区上方的多晶硅被蚀刻掉以形成延伸栅极和分离电极。通过调节分流电极上的偏压可以减轻漏极附近的电场集中。 FALDMOS和FSLDMOS采用0.35- $\mu \text{m}$ BCD技术制造，展示了沟槽刻蚀、多晶硅填充等关键工艺。实验结果表明，FALDMOS的$\text{R}_{ \mathrm{\scriptscriptstyle ON},sp}$仅为9.3 $\text{m}\Omega \cdot $ mm2，而传统LDMOS为36.2 $\text{m}\Omega \cdot $ mm2，在相同的 BV 36 V 的情况下减少了 74.3%。 而且，在相同面积下，FALDMOS的电流密度是传统LDMOS的五倍。与FALDMOS相比，FSLDMOS的BV提高了66%。