Stereo matching is an essential topic in computer vision. However, the high complexity and massive computation restrict its applicability in real-time. This brief presents a pixel-level pipeline coprocessor for configurable binocular stereo rectification, region-optimized semi-global matching (SGM), left-right consistency checking (LRC), and disparity refinement. The contributions are summarized as follows: 1) Instead of storing the entire image of a large number of lines, the buffer size can be significantly reduced by the adjustment range computed according to the pre-calibrated coefficients. 2) An approximate divider with Newton iterations can reach the precision of 10−7 for high accuracy rectification with low latency. 3) A four-layer parallel two-stage pipeline is leveraged to address the computational bottleneck of the SGM, i.e., cost aggregation. 4) The pseudo-dual-port SRAMs and stacks mechanism solve the problem of inverse pixel flow in hole filling with low resource consumption. Finally, the proposed architecture is implemented on an Intel Stratix-IV FPGA and can process 144 frames ( 1024×7681024\mathbf {\times }768 -pixel) per second at a maximum working frequency of 113.13 MHz.

中文翻译：

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用于立体视觉的可配置图像校正和视差细化


立体匹配是计算机视觉中的一个重要课题。然而，高复杂度和海量计算限制了其实时适用性。本简介介绍了一种像素级管道协处理器，用于可配置的双目立体校正、区域优化的半全局匹配 (SGM)、左右一致性检查 (LRC) 和视差细化。贡献总结如下： 1）不是存储大量行的整个图像，而是可以通过根据预校准系数计算的调整范围来显着减小缓冲区大小。 2）采用牛顿迭代的近似除法器可以达到10−7的精度，实现低延迟的高精度校正。 3)利用四层并行两级流水线来解决SGM的计算瓶颈，即成本聚合。 4）伪双口SRAM和堆栈机制解决了填孔中的逆像素流问题，资源消耗低。最后，所提出的架构在 Intel Stratix-IV FPGA 上实现，每秒可处理 144 帧（1024×7681024\mathbf {\times }768 像素），最大工作频率为 113.13 MHz。