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AES S-Box Hardware With Efficiency Improvement Based on Linear Mapping Optimization
IEEE Transactions on Circuits and Systems II: Express Briefs ( IF 4.4 ) Pub Date : 2022-06-23 , DOI: 10.1109/tcsii.2022.3185632
Ayano Nakashima 1 , Rei Ueno 1 , Naofumi Homma 1
Affiliation  

This brief presents a new Advanced Encryption Standard (AES) S-Box hardware design based on linear mappings optimized by combining multiplicative and exponential offsets. Generally, the performance of S-Box with composite field representations depends on the structure of linear mappings (i.e., transformation matrices) between the polynomial field and composite field before and after the S-Box. So far, multiplicative and exponential offsets have been applied only to Boyar-Peralta type S-Box variants for optimizing the transformation matrix. In this brief, we apply the offset methods to another S-Box based on the redundant Galois field arithmetic and evaluate the performance by logic synthesis. Specifically, we design and evaluate two new types of S-Box hardware: one for encryption only (ENC) and the other for both encryption and decryption (ENC/DEC). The evaluation result confirms that the proposed ENC and ENC/DEC S-Boxes achieve a performance up to 8.7% and 28.8% higher, respectively, than the highest-performing conventional ones in terms of the area timing (AT) product.

中文翻译:

基于线性映射优化提高效率的AES S-Box硬件

本简介介绍了一种新的高级加密标准 (AES) S-Box 硬件设计,该设计基于通过组合乘法偏移和指数偏移而优化的线性映射。通常,具有复合域表示的 S-Box 的性能取决于 S-Box 前后多项式域和复合域之间的线性映射(即变换矩阵)的结构。到目前为止,乘法和指数偏移仅应用于 Boyar-Peralta 类型的 S-Box 变体以优化变换矩阵。在这篇简报中,我们将偏移方法应用于另一个基于冗余伽罗瓦域算法的 S-Box,并通过逻辑综合来评估性能。具体来说,我们设计和评估了两种新型 S-Box 硬件:一个仅用于加密 (ENC),另一个用于加密和解密 (ENC/DEC)。评估结果证实,所提出的 ENC 和 ENC/DEC S-Box 在区域计时 (AT) 产品方面的性能分别比性能最高的传统产品高出 8.7% 和 28.8%。
更新日期:2022-06-23
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