This brief presents four small-area SAR ADCs with a resolution from 8 to 11 bits. Two area-saving techniques are utilized. First, the DAC layout is implemented with custom designed unit-length capacitors, which are optimized for each resolution to minimize the chip area. Second, dynamic logic is applied to the 8-bit design to further reduce the number of transistors and save area. Fabricated in 65 nm CMOS, the 8/9/10/11-bit SAR ADCs only occupy 20×21μm20\times 21\,\,\mu \text{m} , 20×36μm20\times 36\,\,\mu \text{m} , 36×36μm36\times 36\,\,\mu \text{m} and 36×36μm36\times 36\,\,\mu \text{m} , respectively. At 10 MHz sampling rate, their measured ENOB is 7.5, 8.3, 9.1 and 9.8 bits with an SFDR of 65.4 dB, 67.4 dB, 78.0 dB and 76.5 dB, respectively. Compared to prior-art, these designs achieve the smallest areas for the achieved ENOBs.

中文翻译：

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具有紧凑单位长度 DAC 布局的小面积 SAR ADC


本简介介绍了四种分辨率为 8 至 11 位的小面积 SAR ADC。采用了两种节省面积的技术。首先，DAC 布局是通过定制设计的单位长度电容器实现的，这些电容器针对每种分辨率进行了优化，以最大限度地减少芯片面积。其次，将动态逻辑应用于8位设计，进一步减少晶体管数量并节省面积。采用 65 nm CMOS 制造，8/9/10/11 位 SAR ADC 仅占用 20×21μm20\times 21\,\,\mu \text{m} 、 20×36μm20\times 36\,\,\mu \text{m} 、 36×36μm36\times 36\,\,\mu \text{m} 和 36×36μm36\times 36\,\,\mu \text{m} 分别。在 10 MHz 采样率下，测得的 ENOB 为 7.5、8.3、9.1 和 9.8 位，SFDR 分别为 65.4 dB、67.4 dB、78.0 dB 和 76.5 dB。与现有技术相比，这些设计实现了所实现的 ENOB 的最小面积。