This brief presents a low-cost blind oversampling CDR (Clock Data Recovery) architecture that obviates the need of a dedicated clock generator or oversampling clock at the receiver end of a high-speed serial link. The proposed CDR reuses an existing at-speed clock available in the system. It deploys a sampler circuit at the input coupled to a data storage and control block that frames the serial input into a parallel output data frame along with the recovered clock. The all-digital CDR algorithm tracks clock impairments and takes appropriate action when UI (Unit Interval) boundaries are violated. Samples obtained at non-uniform time stamps near rise & fall clock edges are used to determine valid data captures. Unlike conventional oversampling CDRs, it achieves high jitter tolerance (JTOL) without storing and post processing multiple data word samples. The absence of a FIFO and elastic buffer in the design greatly reduces design size. As a result, the proposed technique achieves low power, wide-range operation with minimal hardware overhead and design implementation effort while delivering performances at par with conventional approaches. A 2Gbps CDR design in 28nm technology is demonstrated with digital area 0.00063mm2 and power 0.88mW.

中文翻译：

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用于使用单相输入时钟的串行链路的低成本 0.00063mm2、0.44pJ/b、2Gb/s 全数字全合成 CDR


本简介介绍了一种低成本盲过采样 CDR（时钟数据恢复）架构，该架构无需在高速串行链路的接收器端使用专用时钟发生器或过采样时钟。所提出的 CDR 重用了系统中可用的现有全速时钟。它在输入端部署了一个采样器电路，耦合到数据存储和控制块，将串行输入与恢复的时钟一起构建为并行输出数据帧。全数字 CDR 算法跟踪时钟损伤，并在违反 UI（单位间隔）边界时采取适当的措施。在时钟上升沿和下降沿附近的非均匀时间戳处获得的样本用于确定有效的数据捕获。与传统的过采样 CDR 不同，它无需存储和后处理多个数据字样本即可实现高抖动容限 (JTOL)。设计中没有 FIFO 和弹性缓冲器，大大减小了设计尺寸。因此，所提出的技术以最小的硬件开销和设计实现工作实现了低功耗、宽范围操作，同时提供与传统方法相当的性能。演示了采用 28nm 技术的 2Gbps CDR 设计，数字面积为 0.00063mm2，功耗为 0.88mW。