A floating-body transistor based two stages power amplifier (PA) with lateral NPN based bandgap voltage reference (BVR) is implemented in a 130 nm Silicon-On-Insulator (SOI) CMOS process for sub-6GHz 5G applications. Floating-body (FB) transistors instead of traditional body-contacted (BC) transistors have been adopted in driver stage and power stage amplifiers of the proposed PA. On-chip input and output transformer baluns (TB) are customized designed for this PA which can realize impedance matching. Split push-pull structure is adopted in both driver stage and power stage with inter-stage matching networks. Incorporating bonding wire multi-physics models into input and output matching and power gain temperature compensation, the proposed PA can achieve maximum 25.6 dB power gain, 22.2 dBm output power and 28% power added efficiency (PAE) at 1 dB compression point (OP-1dB). The 3 dB bandwidth of the proposed PA is from 4.3 GHz to 6.4 GHz and the core size is 0.59 mm2. When the proposed PA is used for IEEE 802.11ac application and measured at VHT80 MCS9 (80MHz, 256-QAM), it can achieve 21.4 dBm output power and 24.8% PAE at 5.5 GHz operating frequency with −36 dB error vector magnitude (EVM).

中文翻译：

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用于 SOI CMOS 130-nm 工艺中低于 6-GHz 5G 应用的基于浮动体晶体管的功率放大器

基于浮体晶体管的两级功率放大器 (PA) 具有基于横向 NPN 的带隙电压基准 (BVR)，在 130 nm 绝缘体上硅 (SOI) CMOS 工艺中实现，用于低于 6GHz 的 5G 应用。浮体 (FB) 晶体管代替传统的体接触 (BC) 晶体管已被用于所提议的 PA 的驱动级和功率级放大器。片上输入和输出变压器巴伦（TB）是为此PA定制设计的，可以实现阻抗匹配。驱动级和功率级均采用分体式推挽结构，级间匹配网络。将键合线多物理模型结合到输入和输出匹配以及功率增益温度补偿中，所提出的 PA 可以实现最大 25.6 dB 功率增益，22。2 dBm 输出功率和 28% 功率附加效率 (PAE) 在 1 dB 压缩点 (OP-1dB)。提议的 PA 的 3 dB 带宽为 4.3 GHz 至 6.4 GHz，核心尺寸为 0.59 mm2。当建议的 PA 用于 IEEE 802.11ac 应用并在 VHT80 MCS9（80MHz，256-QAM）下测量时，它可以在 5.5 GHz 工作频率下实现 21.4 dBm 输出功率和 24.8% PAE，误差矢量幅度 (EVM) 为 -36 dB .