This brief presents an input buffer based on AC-coupled flipped source follower (SF) for a 12-bit 8-GS/s time-interleaved (TI) ADC. The flipped SF can drive the ADC’s sampling capacitance with high linearity because the input MOS’s drain current is almost independent of the load capacitance. In addition, the inherent feedback reduces the input buffer’s output impedance, which improves the bandwidth when driving the complex wiring network of TI ADCs. The proposed AC-coupling structure enlarges the input signal range of the flipped SF extensively, making it practical to be used for high-speed ADCs. A compensation capacitor is used to compensate for the nonlinear parasitic capacitance of the input MOS to further improve the linearity. An 8-channel 12-bit 8GS/s TI ADC prototype with the proposed input buffer is implemented in a 28-nm mixed-signal CMOS process. Measured results show that the input bandwidth of the input buffer exceeds 6 GHz with 137-mW power supply. The ADC achieves SFDR of 68 dBFS and SNDR of 54.9 dB with 3.9-GHz, −1-dBFS input signal under 8-GS/s sampling rate. The total power consumption of the ADC is 1.05 W.

中文翻译：

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基于交流耦合翻转源极跟随器的 6GHz 带宽输入缓冲器，用于 28nm CMOS 中的 12 位 8GS/s ADC

本简介介绍了一种基于交流耦合翻转源极跟随器 (SF) 的输入缓冲器，适用于 12 位 8-GS/s 时间交错 (TI) ADC。翻转的 SF 可以驱动 ADC 的采样电容，具有高线性度，因为输入 MOS 的漏极电流几乎与负载电容无关。此外，固有反馈降低了输入缓冲器的输出阻抗，从而提高了驱动 TI ADC 复杂布线网络时的带宽。所提出的交流耦合结构极大地扩大了翻转SF的输入信号范围，使其可用于高速ADC。补偿电容用于补偿输入MOS的非线性寄生电容，进一步提高线性度。具有所建议输入缓冲器的 8 通道 12 位 8GS/s TI ADC 原型在 28-nm 混合信号 CMOS 工艺中实现。测量结果表明，输入缓冲器的输入带宽超过 6 GHz，电源为 137-mW。该 ADC 在 8-GS/s 采样率下实现 68 dBFS 的 SFDR 和 54.9 dB 的 SNDR，3.9 GHz、-1-dBFS 输入信号。ADC 的总功耗为 1.05 W。