In this work, we propose a ferroelectric FET(FeFET) time-domain compute-in-memory (TD-CiM) array as a homogeneous processing fabric for binary multiplication-accumulation (MAC) and content addressable memory (CAM). We demonstrate that: i) the XOR(XNOR)/AND logic function can be realized using a single cell composed of 2FeFETs connected in series; ii) a two-phase computation in an inverter chain with each stage featuring the XOR/AND cell to control the associated capacitor loading and the computation results of binary MAC and CAM are reflected in the chain output signal delay, illustrating full digital compatibility; iii) comprehensive theoretical and experimental validation of the proposed 2FeFET cell and inverter delay chains and their robustness against FeFET variation; iv) the homogeneous processing fabric is applied in hyperdimensional computing to show dynamic and fine-grain resource allocation to accommodate different tasks requiring varying demands over the binary MAC and CAM resources.

中文翻译：

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一种使用铁电时域内存计算的矩阵向量乘法和关联搜索的齐次处理结构

在这项工作中，我们提出了一种铁电 FET (FeFET) 时域内存计算 (TD-CiM) 阵列作为二进制乘法累加 (MAC) 和内容可寻址存储器 (CAM) 的同质处理结构。我们证明： i) XOR(XNOR)/AND 逻辑功能可以使用由串联的 2FeFET 组成的单个单元来实现；ii) 逆变器链中的两相计算，每个阶段都具有 XOR/AND 单元以控制相关的电容器负载，二进制 MAC 和 CAM 的计算结果反映在链输出信号延迟中，说明了全数字兼容性；iii) 对所提出的 2FeFET 单元和逆变器延迟链及其对 FeFET 变化的鲁棒性进行综合理论和实验验证；