In this paper, heavy-ion single-event effects studies are investigated on a 0.2 μm Double silicon-on-insulator (DSOI) 4k bit Static Random Access Memory (SRAM). The back gate bias is used to adjust the single event upset (SEU) rate of the SRAM circuit. Experimental results show that applying a -5 V bias to the back gate of nMOSFETs can reduce the SEU cross section by 31 % ~ 62 %, and the SEU rate by 61 %. While applying to the back gate of both nMOSFETs and pMOSFETs a 5 V bias can increase the SEU cross section by 43 % ~ 298 %, and the SEU rate by 3 orders of magnitude. The SEU rate is calculated using OMERE software under the GEO orbit with a 3 mm aluminum shielding condition. To further analyze the cause of this phenomenon, TCAD simulation and DSOI MOSFETs test were introduced in this paper. Results show that applying a negative bias to the back gate of nMOSFETs will reduce the single particle transient (SET) and increase the threshold voltage of nMOSFETs, which makes the SRAM cell more tolerant to SEU; while applying a positive bias to the back gate of pMOSFETs will decrease the drive current of pMOSFETs, which makes the SRAM cell more sensitive to SEU.

本文在 0.2 μm 双绝缘体上硅 (DSOI) 4k 位静态随机存取存储器 (SRAM) 上研究了重离子单粒子效应研究。背栅偏压用于调整 SRAM 电路的单事件翻转 (SEU) 率。实验结果表明，对nMOSFET的背栅施加-5 V的偏压，可以使SEU截面减少31%~62%，SEU率降低61%。在对 nMOSFET 和 pMOSFET 的背栅施加 5 V 偏置时，可以将 SEU 横截面增加 43 % ~ 298 %，并将 SEU 率增加 3 个数量级。SEU 率是使用 OMERE 软件在 GEO 轨道下以 3 mm 铝屏蔽条件计算的。为了进一步分析造成这种现象的原因，本文介绍了TCAD仿真和DSOI MOSFETs测试。结果表明，对 nMOSFET 的背栅施加负偏压会降低单粒子瞬态 (SET) 并提高 nMOSFET 的阈值电压，从而使 SRAM 单元对 SEU 的耐受性更强；而对 pMOSFET 的背栅施加正偏压会降低 pMOSFET 的驱动电流，从而使 SRAM 单元对 SEU 更加敏感。