This work addresses the reliability of different architectures of novel high-density multi-gate transistors manufactured in a 40 nm embedded non-volatile memory process technology. The multi-gate architectures are based on lateral transistors integrated in deep trenches built alongside the main planar transistor. These architectures increase the conduction channel width with a weak impact on the footprint. A reliability study based on AC stress tests is carried out to monitor the multi-gate oxide degradation and in particular the interaction between planar and vertical oxides is highlighted. Finally, a benchmark of stress immunity, among the three studied multi-gate architectures, is presented.

这项工作解决了采用 40 nm 嵌入式非易失性存储器工艺技术制造的新型高密度多栅极晶体管的不同架构的可靠性。多栅极架构基于集成在与主平面晶体管一起构建的深沟槽中的横向晶体管。这些架构增加了传导通道宽度，但对占位面积的影响很小。进行了基于交流应力测试的可靠性研究，以监测多栅氧化物的退化，特别是突出了平面和垂直氧化物之间的相互作用。最后，介绍了三种研究的多门架构中的压力抗扰度基准。