ABSTRACT

The demand for cost, power and area-efficient de-noising filter is increasing day by day, because of its remarkable performance in various image processing applications. In this paper, a variable-node shift-based median filter is designed for achieving low power and area utilisation. Here, the proposed design encompasses a Max Tree Extraction (MTE) unit in conjunction with various devices, like comparators, variable-node shift generators, token generators, and noise detector units, which enable low hardware requirement and minimise the power consumption. The proposed model lessens the need of complex operations, like rank generation, rank calculation and median selection. Moreover, the proposed median filter is structured by Xilinx software and the hardware implementation is done by FPGA (Virtex 7 ×C7VX980 FPGA). Additionally, the proposed model is evaluated for different test images at various noise levels. The performance of the proposed median filter design is analysed under peak signal to noise ratio (PSNR), mean square error (MSE), power, delay and area. The experimental results show that the overall performance of the proposed method is superior to the state-of-art technologies.

摘要

由于其在各种图像处理应用中的卓越性能，对成本、功耗和面积高效的去噪滤波器的需求日益增加。在本文中，设计了一种基于可变节点移位的中值滤波器，以实现低功耗和面积利用率。这里，所提出的设计包括最大树提取（MTE）单元以及各种设备，如比较器、变量节点移位生成器、令牌生成器和噪声检测器单元，从而实现低硬件要求并最大限度地降低功耗。所提出的模型减少了复杂操作的需要，例如排名生成、排名计算和中值选择。此外，所提出的中值滤波器由Xilinx软件构建，硬件实现由FPGA（Virtex 7×C7VX980 FPGA）完成。此外，针对不同噪声水平下的不同测试图像评估所提出的模型。在峰值信噪比（PSNR）、均方误差（MSE）、功率、延迟和面积下分析了所提出的中值滤波器设计的性能。实验结果表明，该方法的整体性能优于现有技术。