A new method for the generation of pseudo-random bits, based on a coupled-linear congruential generator (CLCG) and two multistage variable seeds linear feedback shift registers (LFSRs) is presented. The proposed algorithm dynamically changes the value of the seeds of each linear congruential generator (LCG) by utilizing the multistage variable seeds LFSR. The proposed approach exhibits several advantages over the pseudo-random bit generator (PRBG) methods presented in the literature. It provides low hardware complexity and high-security strength while maintaining the minimum critical path delay. Moreover, this design generates the maximum length of pseudo-random bit sequence with uniform clock latency. Furthermore, to improve the critical path delay, one more architecture of PRBG is proposed in this work. It is based on the combination of coupled modified-LCG with two variable seeds multistage LFSRs. The modified LCG block is designed by the two-operand modulo adder and XOR gate, rather than the three-operands modulo adder and shifting operation, while it maintains the same security strength. The clock gating network (CGN) is also used in this work to minimize the dynamic power dissipation of the overall PRBG architecture. The proposed architectures are implemented using Verilog HDL and further prototyped on commercially available field-programmable gate array (FPGA) devices Virtex-5 and Virtex-7. The realization of the proposed architecture in this FPGA device accomplishes an improved speed of PRBG, which consumes low power with high randomness compared to existing techniques. The generated binary sequence from the proposed algorithms has been verified for randomness tests using NIST statistical test suites.

提出了一种基于耦合线性同余发生器 (CLCG) 和两个多级可变种子线性反馈移位寄存器 (LFSR) 的伪随机位生成新方法。所提出的算法利用多级变量种子 LFSR 动态改变每个线性同余生成器 (LCG) 的种子值。与文献中介绍的伪随机位生成器 (PRBG) 方法相比，所提出的方法具有多项优势。它提供低硬件复杂性和高安全强度，同时保持最小的关键路径延迟。此外，该设计生成具有统一时钟延迟的最大长度的伪随机位序列。此外，为了改善关键路径延迟，在这项工作中提出了另一种 PRBG 架构。它基于耦合修改 LCG 与两个可变种子多级 LFSR 的组合。修改后的LCG块由二操作数模加器和异或门设计，而不是三操作数模加器和移位操作，同时保持相同的安全强度。时钟门控网络 (CGN) 也用于这项工作，以最大限度地减少整个 PRBG 架构的动态功耗。所提出的架构使用 Verilog HDL 实现，并在商用现场可编程门阵列 (FPGA) 设备 Virtex-5 和 Virtex-7 上进一步原型化。在此 FPGA 设备中实现所提出的架构提高了 PRBG 的速度，与现有技术相比，它具有低功耗和高随机性。