The threshold voltage of rectangular p-type triple-gate junctionless transistors (JLTs) is studied experimentally using the transconductance derivative (dg_m/dV_g) method, after correcting the drain current from the impact of series resistance. The effect of series resistance on the dg_m/dV_g behavior is highlighted. In the investigated devices, the high series resistance affects the dg_m/dV_g behavior more than the short-channel effects. The results show that, in addition to the flat-band voltage, for the first time two threshold voltages V_th1 and V_th2 are observed within the partial depletion region in devices with channel length varying from 95 to 25 nm. Numerical simulations of the holes density distribution reveal the absence of corner effects due to the unique bulk neutral conduction, whereas V_th1 and V_th2 correspond to the threshold voltages of the side gates and top gate, respectively. The correct extraction of the flat-band voltage has been confirmed with numerical simulations of the holes density distribution. Experimental measurements of p-type JLTs with variable being the fin width indicate that the threshold voltages V_th1 and V_th2 are due to the different interface states density at the side and top gates.

在校正串联电阻影响的漏极电流后，使用跨导导数 (dg _m /dV _g ) 方法对矩形 p 型三栅极无结晶体管 (JLT) 的阈值电压进行了实验研究。强调了串联电阻对 dg _m /dV _g行为的影响。在所研究的器件中，高串联电阻对 dg _m /dV _g行为的影响大于短沟道效应。结果表明，除了平带电压之外，还首次出现了两个阈值电压 V _th1和 V _th2在通道长度从 95 到 25 nm 不等的器件的部分耗尽区内观察到。空穴密度分布的数值模拟表明，由于独特的体中性传导，不存在角效应，而 V _th1和 V _th2分别对应于侧栅和顶栅的阈值电压。通过空穴密度分布的数值模拟证实了平带电压的正确提取。对鳍片宽度可变的 p 型 JLT 的实验测量表明，阈值电压 V _th1和 V _th2是由于侧栅和顶栅的界面态密度不同。