This paper proposes a new discrete cosine transform (DCT) processor. The micro-rotation section of the architecture is based on a shared-resource improved coordinate rotation digital computer (CORDIC) unit, in an enhanced scalable DCT engine. To reduce the resources, and utilization area all micro-rotation operations have implemented as one united block in overlapped form. Using one processing element, the memory-based architecture has reduced the power consumption. Inputs and outputs of the processor are in-order which can be taken into account as an advantage for the proposed design. The processor has a low-complexity and distributed controller. Furthermore, due to the shared-resource implementation of CORDIC-II unit, by reduction of adding, shifting operations both in size, and number, the processor has high capabilities in short word lengths in comparison with state-of-the-art DCT processors. Compared to existing prominent DCT processors, the proposed processor achieves better results with limited hardware resources.

本文提出了一种新的离散余弦变换（DCT）处理器。该架构的微旋转部分基于共享资源改进的坐标旋转数字计算机 (CORDIC) 单元，在增强的可扩展 DCT 引擎中。为了减少资源和利用面积，所有的微旋转操作都以重叠的形式作为一个联合块实施。使用一个处理元件，基于内存的架构降低了功耗。处理器的输入和输出是有序的，可以将其视为所提出设计的优势。该处理器具有低复杂度的分布式控制器。此外，由于 CORDIC-II 单元的共享资源实现，通过减少大小和数量上的加法、移位操作，与最先进的 DCT 处理器相比，该处理器在短字长方面具有很高的能力。与现有突出的 DCT 处理器相比，所提出的处理器在有限的硬件资源下取得了更好的效果。